Prosilog announces Magillem V3.0 supporting Eclipse platform

Cergy, France – May 25, 2005 – Prosilog SA, a leading provider of innovative solutions for SoC design and verification, announces a major new release 3.0 of its Magillem platform based design tool. This release combines advanced features to enable faster platform based designs with the support of the Eclipse* open development environment.

Magillem V3.0 is leveraging the powerful plug-ins capabilities from the Eclipse framework combined with an internal data structure API in order to deliver a consistent user interface for the designer. Within Magillem V3.0, developers still benefit from the SPIRIT Packager module, that provides capabilities to generate a SPIRIT** 1.1 compliant XML from their current VHDL/Verilog IPs source and specifications files.

Moreover, as a SPIRIT based design environment, Magillem V3.0 ensures that all requirements for IP reuse and integration are being taken into account. Creating and manipulating SPIRIT attributes of a design is handled through schematic or scripting interfaces.

Integrating third-party generators becomes easier thanks to the SPIRIT schema; designers have the capability to use their already existing generators associated to their IPs, thus getting a greater flexibility and automation to fit with their current design practices.

As an active participant in the SPIRIT ESL Working Group, defining the SPIRIT TLM specification, Prosilog is currently adapting MagillemÒ and the SPIRIT Packager module to support SPIRIT 2.0 XML specification when it is released.

“ With the latest release of Magillem, our customers have a solid and powerful multi-platform environment which allows them to package, interconnect IPs and generate their design,” says Marcel Saussay CEO of Prosilog.

About Prosilog SA
 
Prosilog SA is developing innovative RTL & System Level Design EDA tools, as well as soft IP cores, which help SoC designers to reduce the cycle time of their product design.

The Prosilog’s environment for specifying, verifying and implementing complex SoC’s, handles system descriptions both at transactional and RTL levels and therefore, facilitates the SoC early architecture exploration phase.
Its graphical front-end, allows the easy integration of different IP blocks, the automatic interface and interconnect generation between IP's as well as the insertion of verification modules.
The IP Creator module enables the fast generation of a VCI, or OCP interface, making it easy to create a common interface for any IP portfolio.
For additional information, please visit www.prosilog.com

(*) Eclipse Platform: www.eclipse.org

(**) SPIRIT: Structure for Packaging, Integrating and Re-using IP within Tool flows:  www.spiritconsortium.org

Magillem and Nepsys are registered trademarks of Prosilog SA.
All other trademarks are the property of their respective holders.