AccelChip Facilitates Sensor Array Processing with New SVD Matrix Factorization DSP IP Core

MILPITAS, CA, June 1, 2005 – Building upon its recent releases of matrix inversion and factorization parameterized cores, AccelChip Inc., the industry’s only provider of automated flows from MATLAB® algorithms to silicon, has added a singular value decomposition (SVD) core generator to its AccelWare® Advanced Math Toolkit.  This new core generator makes the process of implementing sensor array processing algorithms containing SVD matrix inversion and factorization into FPGAs and ASICs much easier and will dramatically reduce development times.

Computationally intensive, sensor array processing enhances the ability to localize sources of energy, track sources, and mitigate the effects of noise and interference in challenging physical environments.  Sensor array processing relies on the implementation of linear algebra-based, high-performance algorithms.  Singular value decomposition is a highly robust algorithm that can always produce a result, even when other matrix inversion methods fail. The specific algorithm used in the AccelWare SVD core is designed to exploit the highly parallel structures available in FPGA and ASIC implementations.

“Much of the algorithm development for optimum sensor array processing takes place in the MATLAB environment,” said Professor Kevin Buckley, Signal Processing Researcher and faculty member at Villanova University and the University of Minnesota. “Thus, AccelChip is uniquely positioned to contribute to growth in the effective application of sensor array processing techniques.”

“AccelChip Inc. has a leadership position in IP cores that directly implement matrix operations for sensor array processing, wireless communications, and signal processing,” said Michael Bohm, CTO and vice president of Product Development, AccelChip Inc.  “Working closely with key customers, we have developed our advanced AccelWare linear algebra cores to meet their design specific requirements for fixed-point, hardware implementations of matrix inversion and factorization.”  

The SVD core is included in the AccelWare Advanced Math Toolkit, along with matrix factorization and inversion cores using the QR and Cholesky decomposition techniques.

About AccelWare DSP Core Generators Toolkits
AccelWare are DSP IP core generators that provide a direct path to hardware implementation for complex MATLAB toolbox and built-in functions. Each generator is capable of creating multiple micro-architectures and offer implementation-specific parameters to tailor the core to market and design specific requirement.  When combined with AccelChip DSP Synthesis, these unique toolkits have been customer proven to save months off traditional RTL design flows for ASIC and FPGA development, while delivering exceptional quality of results and maintaining MATLAB as a single golden source.

AccelChip currently offers four toolkits for communications, signal processing, building blocks, and advanced math.

About the Company
AccelChip Inc. provides solutions for digital signal processing (DSP) design that enable customers to rapidly explore the architectural design space and implement algorithms in FPGAs and ASICs.  The company’s complete solutions include a comprehensive DSP design infrastructure, DSP intellectual property, and technology adoption services that invest in the transfer of knowledge to customers.  AccelChip’s proven solutions integrate the domain-specific DSP design environment (MATLAB) with industry-standard hardware design flows from Aldec, Altera, Cadence, Mentor Graphics, Synplicity, Synopsys, The MathWorks, and Xilinx.  Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip’s Web address is www.accelchip.com.

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AccelChip and AccelWare are registered trademarks of AccelChip Inc.  All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies.