Poseidon automates the generation of hardware accelerator modules for Xilinx Virtex-4 FPGAs

Triton Tool suite creates APU-compatible Fabric Co-processor Modules,  interfaces and the attending software drivers – automatically! 

San Jose, CA – June 13, 2005 – Poseidon Design Systems today announced the adaptation of its Triton Tool suite for compatibility with the Xilinx ISE™ tool flow to enable Virtex™-4 FX FPGA designers using the Auxiliary Processor Unit (APU) controller to automatically generate hardware accelerator modules. By making the Triton tools complimentary to the ISE tool flow, Poseidon has streamlined the identification of system performance bottlenecks and the mechanics of partitioning and implementing hardware acceleration co-processors that utilize the APU controller. 

The APU controller provides a flexible high-bandwidth interface between the reconfigurable logic in the FPGA fabric and the instruction pipeline of the integrated IBM PowerPC™ 405 CPU. Fabric co-processor modules (FCMs) implemented in the FPGA fabric connect to the embedded PowerPC processor through the APU controller interface to act as user-defined hardware accelerators. These hardware accelerators operate as extensions to the PowerPC 405, thereby enabling the offloading of the CPU from demanding computational tasks.

“Hardware acceleration is the premise upon which Poseidon was founded,” said Ravi Janak, president and CEO of Poseidon Design Systems. “So we were delighted to discover that Xilinx had developed the APU controller to address this very important issue, and we moved immediately toward the adaptation of our tool suite to the Xilinx ISE tool flow to accommodate the rapid, automatic generation of co-processors, interfaces and software drivers,” explained Janak.

The Triton Tools environment un-intrusively augments existing FPGA design flows to optimize performance, power, and cost of processor-based architectures. The Triton tool suite comprises two tools: Triton Tuner and Triton Builder. Triton Tuner gives Xilinx FPGA designers the ability to rapidly evaluate their architectures much earlier in the design effort, thus uncovering performance bottlenecks and eliminating costly architectural rework later in the project. Triton Builder enables designers to rapidly and predictability partition their hardware and software, adding sophisticated hardware acceleration modules to accelerate algorithmic computation.

“Poseidon’s Triton Tool suite strikes at the heart of embedded system performance – algorithmic acceleration,” said Farzad Zarrinfar, vice president of Worldwide Sales and Marketing for Poseidon Design Systems. “By providing the ability to effectively identify and analyze system-level performance bottlenecks and then create the dedicated accelerator hardware and drivers to accelerate that performance, Poseidon’s ESL (Electronic System Level) tool suite affords Xilinx FPGA designers invaluable headroom in performance, power and time-to-market for their APU-based designs,” added Zarrinfar.

Compatible with the Platform Studio tool suite included in the Xilinx Embedded Development Kit, the Poseidon-generated hardware accelerators efficiently connect to the PowerPC’s APU interface. By utilizing the APU controller interface, the hardware accelerators enable higher bandwidth data transfer with lower latency as compared to interfacing to a shared bus implementation. Poseidon combines this APU interface with the Poseidon DMA architecture to transfer data in the most effective manner available. For example, large data array transfers to system memory use the DMA construct to make efficient use of the burst mode of the PLB bus; key parameters and cached data are transferred through the APU.

The APU controller is a powerful integration engine. Poseidon will continue developing accelerator architectures that make use of its wide array of capabilities.

“Poseidon’s ESL tools focus on extracting maximum performance from processor-based FPGA designs by identifying and alleviating system performance bottlenecks with hardware accelerators early on in the development cycle,” stated Dan Isaacs, director of Embedded Processor Marketing, Advanced Products Division at Xilinx. “This is consistent with Xilinx vision of enabling embedded developers to accelerate computational-intensive algorithmic routines by utilizing theVirtex-4 FX APU controller.”

About Poseidon Design Systems

Poseidon is an Electronic Design Automation and Service company with offices in Atlanta, GA., San Jose, CA, and Bangalore, India. It was founded in July 2002 to provide products and services for modeling and designing processor-based SoCs. Poseidon's Electronic System Level tools allow users to rapidly analyze, optimize and accelerate a complete SoC system. For additional information about Poseidon Design Systems, visit www.poseidon-systems.com.

Poseidon will be conducting daily seminars demonstrating the Triton Tool suite at DAC 2005 in Anaheim, CA on June 14-16.

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