Structured ASICs deserve serious attention at 90 nm

By Michael Santarini, Senior Editor -- 7/7/2005
EDN

Four years after ASIC vendors introduced their first structured-ASIC devices in response to FPGA vendors eating up their market share, the structured-ASIC market has yet to become a popular choice for logic designs.

But analysts say that the structured-ASIC market is a viable business today and may exceed $1 billion by 2008, as designers add up the cost of 90-nm ASIC design and run up against the hard limitations of FPGAs.

Analysts and structured-ASIC vendors put up good arguments about why you should at least consider structured fabric for your next IC-design project. But you should consider a number of variables—both technical and business—when evaluating FPGAs, structured ASICs, and cell-based ASICs.

Companies market structured ASICs as the midvolume, midprice missing link between fast-turnaround, reprogrammable but low-volume FPGAs and high-cost, high-volume, hard-to-design cell-based ASICs.

A structured device resembles a gate array on steroids. Like gate arrays, structured ASICs have a limited number of designable layers (usually one to six), a low tool and NRE cost, and a turnaround time ranging from days to months. As with gate arrays, silicon vendors have taken care of most of the nasty physical-design effects with prerouted and pretested layers. In most devices, they've also predesigned the clock tree. But structured-ASIC devices offer much larger designable gate counts and much more on-chip memory than gate arrays.

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