ACTEL and HDL Works Announce Optimization of Graphical HDL Design Entry Environment for Actel Design Flow

Companies Also Announce Addition of HDL Works to Actel's EDA Alliance Program

CAMBERLEY, UK and EDE, Netherlands, July 26 -- Actel Corporation (Nasdaq: ACTL) and HDL Works today announced the optimization of HDL Works' EASE design entry tool for Actel's Libero Integrated Design Environment (IDE) design flow. The EASE Graphical HDL Design Entry environment provides a fast and accurate way for design entry, modification and maintenance of VHDL, Verilog and mixed-language designs for FPGAs and ASICs. Furthermore, the two companies announced the addition of HDL Works to Actel's EDA Alliance Program.

An optimized HDL tool flow is important for all Actel customers that produce and maintain complex HDL designs. Siemens is one of those customers that identified this need.

"We've used EASE for implementation of many designs in Actel devices very successfully. The major benefit we experience is the enormous reduction in time necessary for editing, debugging and modifying the HDL code," said Thomas Rode, design manager for Siemens' automotive and drives division in Nurnberg, Germany. "The close integration of the design tools reduces design time and eases the interaction between the different stages of the design flow, which greatly enhances productivity and optimizes exploration of multiple design implementations."

HDL Works has optimized EASE for the Libero IDE flow, offering the Libero users easy access to all features available in EASE via an enhanced and intuitive interface.

"We have customers in many different markets, including the high- reliability segments where Actel FPGAs are a popular choice. This integration offers our mutual customers the right toolset for the ever increasing complexity for high-end FPGA designs," said Willem Gruter, president and CEO of HDL Works.

"We are pleased to partner with HDL Works because EASE complements the Libero IDE and offers the combination of both power and ease of use that FPGA designers value," said Saloni Howard-Sarin, director of antifuse and tools marketing at Actel. "When our customers use EASE, they can save time and money by eliminating costly errors in HDL code. They can then use the RTL generated by EASE in the Libero environment to complete their design."

EASE is a design entry tool that gives users the choice of graphical or text-based HDL entry. This choice provides designers with the perfect combination of using their language of choice while improving productivity by using the power of EASE for documentation, communication, editing, propagating changes through the design hierarchy and exploring different implementations. EASE automatically generates optimized HDL code in either VHDL or Verilog. In addition, it supports industry standard version control environments for design and configuration management.

Pricing and Availability

The EASE tool is available now. Prices begin at $4,200 (U.S.). An evaluation copy can be downloaded from the HDL Works Web site at http://www.hdlworks.com/.

About HDL Works

HDL Works develops and markets high-performance, intuitive tools for complex HDL design across a wide spectrum of applications. Its software products are available on the industry's most popular workstations and personal computer platforms. HDL Works currently holds EASE and HDL Companion in its product portfolio. Headquartered in Ede, The Netherlands, HDL Works is privately held.

About Actel

Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL, and is headquartered at 2061 Stierlin Court, Mountain View, CA, 94043-4655, with regional offices throughout Europe, including the U.K., Germany, France, Italy and Sweden. Telephone: 888-99-ACTEL (992-2835). Internet: http://www.actel.com.

The Actel name and logo are trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners.

SOURCE Actel Corporation

ACTEL and HDL Works Announce Optimization of Graphical HDL Design Entry Environment for Actel Design Flow

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