Hitachi releases IP spec language

Hitachi releases IP spec language
By Chris Edwards, EE Times UK
October 23, 2000 (11:34 a.m. EST)
URL: http://www.eetimes.com/story/OEG20001023S0031

LONDON — Researchers at Hitachi Ltd.'s Central Research Laboratories (Tokyo) have created a way to specify some characteristics of intellectual property (IP) cores, and believe that refinement of those specs will reduce the number of errors introduced into designs that use those cores.

The researchers have defined the object wrapper language (Owl) that they claim provides a more rigorous way of specifying the interfaces between virtual components or IP cores. The language has been designed to represent synchronous interface protocols and uses a syntax based on regular expressions similar to those used in search tools such as grep. This information is combined with a description of the expected signal sequence at each port and a description of how the interface protocol maps onto functions performed by the core.

In an Owl description, several layers of hierarchy define how interfaces behave. The lowest level uses an "alphabet" that matches p ossible line states to a set of I/O ports on the IP core. The port definition uses a Verilog-style syntax and can cover buses as well as single ports.

The alphabet defines the possible states that the core can be in at any one time. On a memory device, for example, the state that delivers an address will need to be created along with another to indicate a wait state and one that pushes the data out onto the bus. Other states may include reset, or no operation at all.

These states are formed into sequences using Owl 'words.' For example, 'read' will typically comprise an address-delivery phase, a wait state and the state that returns data to the client. The Owl word, expressed in regular-expression syntax, combines those states into a sequence. More complex constraints can be represented using additional procedural code.

Finally, an Owl 'sentence' describes which words can be supported by the device at any one time. In simple examples, such as the memory, the sentence simply describes how the me mory can move between the reset, no-operation and read phases.

Typically, the descriptions are transformed by a computer into a state-transition graph, or a graphical timing diagram. Because a tool can extract a state-transition graph easily, the information can be used during simulation to test the behavior of an existing IP core against a prototype for which the designer only has an Owl description, Hitachi said.

Alternatively, it can be used during regression testing to ensure that an implementation of the core in Verilog or VHDL still conforms to the original specification. Hitachi has built a tool to link Owl descriptions to a simulator for verification. A second tool is used to let a designer view how the core is expected to behave. Similar to the timing diagram in a databook, designers can work out how well a prospective core fits into their design.

The team is developing a full working prototype of a design environment called Owl Messenger together with a reuse methodology built around the language.

Chris Edwards is editor of Electronics Times, a sister newspaper of EE Times in the United Kingdom.