|
||||||||||
Cadence Aligns Capabilities for Consumer and Mobile Applications to Support ARM's Cortex-A8 Processor
Encounter Synthesis, Implementation, and Verification with Cadence Services Enable Flexible Path to High-Performance, Low-Power Design for New ARM Processor
SAN JOSE, Calif . , October 4, 2005 -- Cadence Design Systems, Inc. (NYSE: CDN) (Nasdaq: CDN) today announced the immediate availability of a high-performance design flow for the new ARM® Cortex™-A8 processor. This flow uses the Cadence® Encounter® digital IC design platform incorporating Encounter RTL Compiler synthesis, Encounter Conformal® equivalence checking, and SoC Encounter® RTL to GDSII system. In addition, the company announced the immediate availability of Cadence support and services to improve time to market for ARM Partners implementing very high-performance Cortex-A8 processor-based designs. The ARM Cortex-A8 processor targets digital-entertainment and mobile-communications products with demanding performance, cost and power requirements in conjunction with tight time-to-market constraints. Cortex-A8 customers at 90 and 65 nanometers will be able to leverage the Encounter design flow and Cadence's extensive experience in implementing ARM technology-based SoC designs in order to minimize power, maximize performance, and tape out successful implementations ahead of their competitors. "We are pleased to collaborate with ARM to bring leading-edge SoC design capabilities to their Cortex-A8 Partners," said Jan Willis, senior vice president of Industry Alliances at Cadence. "Our joint program combines engineering and development resources to help our mutual customers speed the completion of advanced digital-entertainment and mobile-communications products. This marks another milestone in our longstanding collaboration with ARM, which now spans over ten years and provides the broadest array of technology and support for ARM processor-based design." "Our ongoing partnership with Cadence continues to produce innovative approaches to enable a faster path to our Partners' successful product introductions," said Mike Inglis, executive vice president of Marketing at ARM. "The capacity and optimization of the Cadence Encounter platform, combined with the ARM Artisan® Advantage-CE library for the Cortex-A8 processor, provides a complete front-to-back flow in high-performance, low-power design." The high-performance design flow leverages the automation techniques of the Cadence Optimization Methodology Kit for ARM Processors that maximize high performance, low power, and small die size. The collaboration will also enhance the ARM-Cadence Encounter Reference Methodology for RTL-to-GDSII synthesis, implementation, and verification of ARM processors. Availability About Cadence
|
Home | Feedback | Register | Site Map |
All material on this site Copyright © 2017 Design And Reuse S.A. All rights reserved. |