Tenison Demonstrates First Solution Reusing HDL RTL in ESL Design

San Jose Calif. – November 21, 2005 – Tenison Design Automation, a company focused on delivering tools for accelerating ESL design, has announced the first public showing of VTOC and the ARM® RealView® SoC Designer with MaxSim™ technology, for incorporating existing RTL into new SystemC ESL designs. The demonstration will be held at the ARM Connected Community Technical Symposium in Paris on 15th November. The software demonstration will encapsulate the complete end user experience when using the tools by demonstrating how existing IP can easily be reused in new ESL design environments at high simulation speeds suitable for design exploration.

Designed to bridge the “Model Gap” that exists in ESL, Tenison’s modeling technology gives designers the ability to move to higher levels of abstraction as well as working in or between different levels. This demonstration will show how the Model Gap can be overcome, and that many models existing today can quickly be re-used to speed new ESL designs.

“System designers adopting ESL techniques need to rapidly create custom model libraries,” said Chris Lennard, ESL Strategic Marketing Manager at ARM. “The integrated flow from VTOC to RealView SoC Designer helps resolve the issue of legacy RTL IP import to the system-modeling environment.”

80 per cent of a typical new ASIC/ASSP design is reuse of existing design IP written in Verilog or VHDL. Reuse of such legacy IP is key to the adoption of Embedded System Level (ESL) design methodologies and tools. The most effective strategy is to use a tool that can take existing RTL and convert it to models in ESL-friendly languages such as C++ or SystemC for import into ESL tools. This means that in order to take advantage of the full capabilities of a system, IP blocks need to be described in SystemC. Yet, this can be a problem when existing designs or the IP blocks from outside vendors exist only in RTL.

“VTOC delivers a tremendous reduction in design time by allowing systems engineers to take advantage of the known good elements in RTL and reuse them in the design of a new system. Using the ARM RealView SoC Designer environment illustrates the ease of inserting, debugging, and simulating the combined models in SystemC,” commented Jeremy Bennett, CTO, Tenison Design Automation. “Combining ease of reuse, fast model performance, and full debug visibility is a huge practical advance in total ESL productivity and performance.”

About the Demonstrations

There will be two demonstrations, one to show the power of VTOC models of RTL in a RealView SoC Designer environment, the second to show how the technology scales to complete multi-core SoC designs. In the first demonstration, the features available through use of VTOC with RealView SoC Designer are demonstrated. In this demonstration a specialized compute engine in RTL is converted for use in the RealView SoC Designer. Tenison VTOC Validate is used to demonstrate the model is correct. The model is then loaded into RealView SoC Designer, and simulated to illustrate:

1. The speed and full accuracy of the RTL model—every register has its correct value at every clock cycle; and
2. Full debug access to the original RTL hierarchy is available—registers and arrays can be read, written and break pointed from within the RealView SoC Designer tool environment.

The second demonstration shows the scalability of this technology to complete SoC designs. The demonstration begins with a complete SoC design captured in the ARM RealView SoC Designer environment. The SoC includes an ARM9™ family processor, AMBA® AHB bus, and several peripheral pieces of IP. Tenison’s VTOC is used to convert an ARM PrimeCell® PL190 interrupt controller from RTL to C++ so that it can be easily included in the design. Tenison’s Validate is once again used to validate that the SystemC version of the PL190 is the same as the RTL version. The C++ PL190 is then inserted into the RealView SoC Designer environment and simulated to illustrate the full accuracy of the RTL model, while maintaining high performance and offering full debug access to the original RTL hierarchy from within the ESL C++ tool environment. The demonstration uses fully functional ARM and Tension systems to emphasis how the increase in productivity can be obtained by reusing existing RTL in new ESL level designs.

Availability and Price

VTOC is available now. For more information, contact Tenison at sales@tenison.com.

About Tenison

Tenison is focused on accelerating electronic system level design by providing the tools and services that enable designers to easily transcend levels of hardware description to achieve the highest performance in models for the accuracy required. The development of complex systems and the integration of software with hardware designs are often constrained by the ability to access a high performance model of the hardware for reuse, verification, or integration. Customers include ST Microelectronics, Conexant Systems, Samsung, Renesas and Skyworks Solutions as well as other Fortune 100 companies. For more information, please visit www.tenison.com.