AccelChip Expands Model-Based Design Solution with Automated Generation of C++ Verification Models

M2C-Accelerator Speeds the Creation and Verification of C Models from MATLAB by Up to 1000x

MILPITAS, CA, January 9, 2006 – AccelChip Inc., the industry’s leading provider of DSP semiconductor IP and algorithmic synthesis software for model-based design, today announced the immediate availability of its 2006.1 version of AccelChip® DSP Synthesis and AccelWare® IP toolkits.  New in 2006.1 is M2C-Accelerator™, an option to AccelChip DSP Synthesis that extends the company’s model-based design solution adding automatic generation of C++ verification models from MATLAB.

M2C Accelerator Converts ‘Golden’ Floating-Point MATLAB Model to Fixed-Point C++
Prior to M2C-Accelerator, companies designing algorithms in MATLAB that experienced excessive verification run times, or required system-level verification in a C environment, were required to manually convert MATLAB models to C. Now, this process is made automatic, fast and error-free with M2C-Accelerator.  Design teams are now able to develop algorithms faster and explore a range of architectural solutions in less time.  The C++ models generated by M2C-Accelerator can be used in MATLAB®, Simulink®, Xilinx System Generator and standalone C verification environments.
 
AccelChip’s M2C-Accelerator customers working on algorithms for applications such as 802.11 and global positioning satellites (GPS) have reported increased verification performance of up to 1000X using M2C-Accelerator in their C-based verification suites and up to 150X in MATLAB simulations when compared to the current fixed-point MATLAB run-times.  
 
M2C-Accelerator provides improved fix-point verification speeds with easy-to-read C++ code,   enabling more design iterations per day in a choice of Model-Based Design environments.  The result is significant time savings for model development and time-to-market advantage over conventional design flows.
 
New AccelProbe Feature Provides Graphical Feedback
To streamline the process of targeting DSP algorithms to ASICs and FPGAs, the 2006.1 release of AccelChip DSP Synthesis also introduces a new feature called AccelProbe. AccelProbe assists the automated floating-point to fixed-point conversion process by providing graphical feedback, including quantized signal-to-noise ratio and quantization histogram reports on any variable in the design. The AccelProbe feature can be used in conjunction with either fixed-point MATLAB or fixed-point C simulations.
 
“Rapid verification at all levels of abstraction is the cornerstone of model-based design,” said Bradley Armstrong, AccelChip’s vice president of engineering. “To reduce risk and development time, it is imperative each model used be a derivative of the golden source so that the end product matches the original specification. Companies spend typically 10x their algorithm development time ensuring the algorithmic model, system-level model, RTL model and gate level models all represent the same design and we have seen many examples where costly re-spins were required when errors were not found up front. With M2C-Accelerator, AccelChip now provides this level of security for companies that rely on C as part of their design flow.”
 
Availability and Pricing
Version 2006.1 of AccelChip DSP Synthesis with IP-Explorer Technology, M2C-Accelerator, Export System Generator and AccelWare IP Generator Toolkits are all now shipping. Current AccelChip maintenance customers will receive the new release at no additional fee. M2C-Accelerator and Export System Generator are available as options to AccelChip DSP synthesis. Pricing for AccelChip DSP Synthesis starts at $15K for a six month time-based license. Pricing for M2C-Accelerator starts at $5K for a six month license.  For more information and pricing, please email sales@accelchip.com.
 
About the Company
AccelChip Inc. is the industry’s leading provider of semiconductor IP and software for MATLAB and Simulink DSP algorithms targeting silicon. The company develops and markets design tools, integrated verification flows, and parametric IP toolkits that combine to automate the development and implementation of DSP algorithms in FPGAs and ASICs.  AccelChip’s proven solution integrates the domain-specific DSP design environment (MATLAB and Simulink) with industry-standard hardware design flows from Aldec, Altera, Cadence, Mentor Graphics, Synplicity, Synopsys, The MathWorks, and Xilinx.  Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip’s Web address is www.accelchip.com. For more information, contact Wendy Truax at (503) 351-0103 or by email at wendy@hipcom.com.