Juniper Networks Selects Denali Verification IP for Design and Verification of its Products

Denali's MMAV™ and PureSpec™-Ethernet Solutions Ensure Correct, Optimal Design of Chip Interfaces, Increasing Verification productivity, Overall Product Quality

PALO ALTO, Calif., January 19, 2006 -- Denali Software today announced that Juniper Networks has selected Denali's MMAV™ and PureSpec™ Ethernet verification intellectual property (IP) for use in the design and verification of Juniper Network products.

Juniper Networks is the leader in enabling secure and assured communications over a single internet protocol (IP) network. Its portfolio of proven networking and security solutions supports the complex scale, security and performance requirements of the world's most demanding networks. Juniper Networks' engineers are using PureSpec at the pre-silicon stage of verification to model and simulate interactions with other devices across industry standard interfaces. PureSpec enables Juniper Networks to ensure correct and optimal design of its chip interfaces, ultimately increasing verification productivity and overall product quality.

"Juniper Networks is noted for their leadership and broad portfolio of innovative solutions in the networking space enabled by leading-edge ASICs and systems designs," says David Lin, vice president of applications engineering at Denali. "We are pleased that Juniper has selected Denali's verification IP products for development of memory and Ethernet interfaces, and we are committed to their continued success."

"Juniper is pleased to work with Denali," adds Haresh Shah, director of Engineering at Juniper Networks. "PureSpec provides us with a robust, feature rich, UNH compliant Ethernet verification suite. This and Denali's industry standard MMAV verification solution for memory interfaces enables us to deploy a staged development environment; this is a unique value that Denali verification IP brings us."

About PureSpec
PureSpec verification IP is the most widely used product for verifying functionality, compliance and interoperability of standard interfaces at the pre-silicon stage of chip or IP core development. PureSpec verification IP includes a configurable bus functional model (BFM), protocol monitor, and complete assertion library for all components in the topology, including the host and one or multiple devices. Composite configurations by port and function are also supported.

PureSpec additionally provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to specifications. The highly integrated nature of PureSpec model behavior and its data generation engine enables a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, accelerating the verification task and productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design.

PureSpec supports a number of standard interfaces, including: PCI Express, Advanced Switching Interconnect (ASI), AXI, AHB, USB2.0, USB OTG, Ethernet, Serial ATA, and CE-ATA.

PureSpec is available for evaluation at: http://www.denali.com/purespec

About Denali
Denali Software Inc. is the world's leading provider of Electronic Design Automation (EDA) and Intellectual Property (IP) products for design and verification of semiconductor chip interfaces. Denali's Databahn™ and Dataplex™ IP products provide control and optimal data throughput for external DRAM and Flash memory devices. The PureSpec™ and MMAV™ verification IP products support all standard interfaces, including DRAM, Flash, PCI Express, ASI, AMBA, USB, Ethernet, Serial ATA, and CE-ATA. Denali's Blueprint product provides complete solution for on-chip register design and management. For more information, visit Denali at http://www.denali.com, call (650) 461-7200 or email info@denali.com.