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National Semiconductor and ARM Release Next-Generation PowerWise Interface Open-Standard SpecificationNew PWI 2.0 Specification provides enhanced two-wire power management interconnect for feature-rich, multi-domain SoCs SANTA CLARA, Calif. AND CAMBRIDGE, UK – Feb. 21, 2006 – National Semiconductor Corporation (NYSE:NSM), and ARM [(LSE: ARM); (Nasdaq: ARMHY)], today announced the availability of the second-generation PowerWise™ interface (PWI) specification, which provides enhanced power management interconnect capability to feature-rich, multi-domain system-on-chips (SoCs) in battery-powered, handheld electronic devices. As an extension of PWI 1.0, PWI 2.0 adds multi-domain capability to address emerging needs of highly integrated SoCs. To extend battery life in handhelds with increased functionality, device manufacturers require advanced power management techniques to dynamically optimize the power consumption of each individual function inside a feature-rich SoC. To enable system designers to efficiently implement such complex designs while maintaining low pin-count, National Semiconductor and ARM, in collaboration with adopters such as Matsushita Electric Industrial, Philips Semiconductor, Samsung Electronics and ST Microelectronics, developed the second-generation PowerWise interface specification. “The PWI 2.0 specification is a significant approach to enable power control efficiencies required for rich multimedia applications with tight power budgets,” said Timo Komulainen, director of Mobile Solutions, Semiconductor Business at Samsung Electronics. “This technology standard will support power-efficient features and key characteristics in the mobile-centric IT industry.” The PWI specification enables rapid deployment of advanced power management solutions in battery-powered handheld electronic devices by providing an open, industry-wide standard for the interconnect between digital SoCs and power management integrated circuits (PMICs). Since the release of the first-generation specification two years ago, the complexity of digital SoC architectures has increased significantly as more and more functionality is embedded into battery-powered devices such as mobile phones, handheld gaming consoles and portable media players. “The PWI 2.0 standard enables simple two-wire implementation of advanced power management technologies such as adaptive voltage scaling and back-biasing in multi-domain architectures,” said Ravindra Ambatipudi, director of Advanced Power Products, National Semiconductor. “PWI 2.0 technology enables device manufacturers to offer new processor-intensive features such as digital multimedia processing and broadcasting with improved battery life while maintaining supply-chain flexibility.” “The PWI 2.0 specification is built upon some of the solid foundations found in the field-proven PWI 1.0 technology. The lessons learned, along with valuable input from leading suppliers in the mobile and consumer industries, have directly resulted in the development of PWI 2.0 technology. This reflects the continued collaboration between ARM and National Semiconductor to be at the forefront of low-power technology design,” said Kevin McIntyre, product manager for Power Management Solutions, ARM. “Power management complexity in battery-operated systems is rapidly increasing. The evolution of the PWI standard is important because it accelerates deployment of innovative power management technologies and solutions.” About the PowerWise Interface Specification The PWI specification defines the required functionality in the PWI-slave; the operating states, the physical interface, the register set, the command set and the data communication protocol for messaging between the PWI-master(s) and the PWI-slave(s). The PWI command set includes PMIC operating state control, register read, register write and voltage adjust commands. The specification also provides a provision for user-defined registers in the PWI-slave. The PWI 2.0 specification maintains the low-power, low-latency, high-bandwidth capabilities of the PWI 1.0 specification, while providing flexibility with an increased PMIC register addressing space, expanded command set and provisions for a multi-point bus with two masters and up to 16 logical PMIC slave connections on one or more PMIC devices. Cost and Availability About National Semiconductor About ARM
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