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QDR Consortium Announces New SRAM Specifications: QDRII+ and DDRII+Newest QDR SRAM Families Target High-Performance Networking and Communications Applications San Jose, CA, March 9, 2006 – Cypress Semiconductor Corp. (NYSE: CY), Integrated Device Technology, Inc. (NASDAQ: IDTI), NEC Electronics Corporation (TSE:6723), Renesas Technology Corp., and Samsung Electronics Co, Ltd. (KSE: 05930) today announced the release of the complete specification for Quad Data Rate™ II+ (QDRII+) and Double Data Rate II+ (DDRII+) SRAM (static random access memory) architectures. Operating at speeds up to 500 MHz, QDRII+ and DDRII+ products will offer improved speeds up to 50 percent faster than existing QDRII and DDRII products. The new high-performance communications memory standard has been developed for network switches, routers and other communications applications. QDRII+ and DDRII+ products will deliver a higher bandwidth than QDRII and DDRII respectively - up to 72 Gbps, while using the same footprints and a 165-pin, FBGA (Fine-pitch Ball Gate Array) package. "The QDRII+ architecture leverages existing infrastructures to create higher performing products that meet changing customer bandwidth requirements," said Brian Metelak, SRAM marketing manager for Cypress. "It is an evolutionary architecture that allows direct transitions to higher frequencies." The QDR and DDR families of SRAM will provide designers with a complete memory solution for almost any network application. QDRII+ devices will have two ports operating independently at twice the selected clock rate, allowing a transfer of four data words in a single clock cycle. The DDRII+ devices will allow double data rate transfers over a common I/O data bus. QDR Consortium members expect to have QDRII+ and DDRII+ samples available in the second quarter of 2006. Specifications for QDRII+ and DDRII+ SRAMs will be publicly available on the QDR SRAM web site (www.qdrsram.com) shortly. About the QDR Co-Development Team
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