Xilinx AccelDSP Synthesis 8.1 Tool Accelerates DSP System Design

New tool and algorithms pack 2X more features at under half the price

SAN JOSE, Calif, April 4, 2006 –Xilinx, Inc. (NASDAQ: XLNX) today announced the immediate availability of the new AccelDSP™ Synthesis 8.1 tool and AccelWare™ DSP libraries of algorithmic intellectual property (IP). This tool and IP package is the first product introduction since the January acquisition of AccelChip, Inc. Xilinx has added new features to the kit that were formerly only available as pay for options, and has reduced the cost by ~60 percent. When combined with the Xilinx System Generator™ for DSP tool, the new AccelDSP Synthesis 8.1 tool provides DSP algorithm and system designers who use MATLAB® and Simulink® design tools with the industry’s most capable design flow for high-performance DSP system design..

For the first time, the new AccelDSP Synthesis tool encapsulates multiple design tools including the AccelChip DSP algorithmic synthesis tool, the M2C™ Accelerator which automatically converts fixed-point MATLAB to C++ for accelerated verification performance, IP-Explorer™ technology used for automatic selection of algorithmic IP based on system parameters, the export to System Generator option which provides a direct link into the System Generator for DSP tool and the AccelWare building blocks IP toolkit, into a single solution.

“Today’s announcement represents our continued investment, support and expansion of the AccelChip customer base,” said Tom Feist, marketing director of Xilinx DSP Tools. AccelDSP’s tight integration into The MathWorks’ Model-Based Design flow helps engineers and designers overcome the limitation of a document-based development process by replacing documents with comprehensive, system-level mathematical models. The models serve as an executable specification enabling designers to simulate and explore architecture implementations as many times as necessary throughout the development process to ensure the end product meets project requirements and system level behavior.”

“Xilinx is making a significant investment in applying Model-Based Design to simplify FPGA-based DSP system development,” said Ken Karnofsky, marketing director for Signal Processing and Communications at The MathWorks, Inc. “Our tools continue to evolve synergistically, giving customers the power and flexibility to design signal processing algorithms and systems in MATLAB and Simulink with a smooth path to optimized hardware implementation on Xilinx FPGAs.”

Today’s announcement represents yet another milestone in the Xilinx DSP roadmap, unveiled in October 2005. Xilinx is now offering the AccelDSP Synthesis tool and DSP libraries of algorithmic intellectual property (IP) as an integrated part of Xilinx XtremeDSP™ solutions. These proven solutions save months over traditional RTL approaches and are application-optimized for digital communications; multimedia, video and image processing (MVI) and defense systems.

Pricing and Availability
The 8.1 AccelDSP Synthesis tool is immediately available for the Windows XP operating system as an option to the Xilinx Integrated Software Environment™ (ISE) tool. Current AccelChip DSP Synthesis maintenance customers will receive AccelDSP at no additional fee. Pricing for AccelDSP Synthesis starts at $30K for a one year, floating, subscription based license. The optional AccelWare signal processing, communication and advanced math IP toolkits are available for $5K each and a composite license for AccelDSP and all AccelWare libraries is available for $40K. For more information about AccelDSP visit www.xilinx.com/AccelDSP

About Xilinx
Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit www.xilinx.com.