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TSMC 65nm Wireless Devices Being Sampled by QUALCOMM; Hot Off TSMC Production Lines, Advanced Devices ''Ring'' for the First Time SAN JOSE, Calif.--April 5, 2006--TSMC today revealed that QUALCOMM is sampling state-of-the-art wireless devices manufactured on TSMC's 65nm process technology. The news comes two months ahead of schedule, and less than a month after the first devices proved their functionality by actually making wireless phone calls. "QUALCOMM is one of the first companies to adopt 65nm for volume production," said Dr. Kenneth Kin, senior vice president of worldwide sales & service of TSMC. "TSMC has distinguished itself in its ability to be the first in the foundry industry to provide leading-edge technology and manufacturing capacity. Through collaboration between QUALCOMM and TSMC, we have been able to engage in product design and process technology development in parallel so as to remove design barrier and ramp new technology to volume production fast." The QUALCOMM Mobile Station Modem(TM) (MSM(TM)) MSM6800(TM) chipset for CDMA2000(R) 1xEV-DO Revision A networks, was delivered to QUALCOMM earlier this year and initial tests indicated that it would be ready for sampling two full months ahead of schedule. In October 2005, TSMC announced it had successfully completed its first CyberShuttle prototype production run for the company's 65 nanometer technology. Five major customers' designs and multiple 3rd party IP designs were on the shuttle. Since then, TSMC has launched four more CyberShuttles with many more customers and IP/library partners actively participated. TSMC's 65nm success builds on the company's industry leading 0.13-micron and 90nm track records. TSMC estimates that the 65nm production will ramp during 2006, and the company will also launch 65nm prototyping shuttles every other month, enabling customers and EDA, IP and library suppliers to prototype and qualify their leading-edge designs. TSMC's 65nm Nexsys(SM) technology is the company's third-generation semiconductor process employing both copper interconnects and low-k dielectrics. It is a 9-layer metal process with core voltages of 1.0 or 1.2 volts, and I/O voltages of 1.8, 2.5 or 3.3 volts. The new technology offering supports a standard cell gate density twice that of TSMC's 90nm Nexsys(SM) process. It also features very competitive 6T SRAM and 1T embedded DRAM memory cell sizes. In addition, this technology offering includes mixed signal and radio frequency functionality to support analog and wireless design, embedded high density memory to support integration of logic and memory and electrical fuse to support customer encryption needs. About TSMC TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to run 65nm customer design prototype wafers. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.
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