Triscend adds 32-bit configurable SoC line

Triscend adds 32-bit configurable SoC line
By Craig Matsumoto, EE Times
August 28, 2000 (10:41 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000828S0015

SAN JOSE, Calif. — Triscend Corp. (Mountain View, Calif.) has released its second family of configurable products. The A7 family uses the same basic architecture as the E5, Triscend's initial family of configurable system-on-a-chip (SoC) devices. But while the E5 was based on an 8-bit 8032 microprocessor core, the A7 is based on the 32-bit ARM7 developed by ARM Ltd.

In addition, Triscend will announce two software partnerships this week, with Wind River Systems Inc. and Embedded Performance Inc., both of which are offering tools for the A7.

Aimed largely at communications applications, the configurable SoC parts integrate a microprocessor, memory, peripherals and Triscend's own system interconnect. The interconnect is the plum of Tri-scend's technology, and a major advantage over other SoC chip architectures, said Barry Chaffin, director of marketing.

"If you take an FPGA and try to put it on a bus, you have to develop a lot of intercon nect circuitry," he said.

In fact, Triscend claims to have a leg up on the other companies that are trying to blend programmable logic and microcontrollers. While numerous PLD vendors have announced plans for such parts, Triscend is shipping them. In addition, the company was able to produce the A7 relatively quickly by borrowing most of the structure of the E5.

"We had the luxury of starting with the same platform because it was designed for a 32-bit processor from the ground up," Chaffin said. "We've rolled out our second family before others have even put out a chip."

Triscend's architecture uses an SRAM-based block of configurable system logic to support programmability. The logic array is fed by the configurable system interconnect, a proprietary high-performance bus that weaves throughout the configurable logic and provides predictable timing in moving data, Triscend said.

Mask costs confronted

Like programmable logic vendors, Triscend is benefiting from increases in ASI C mask costs. One of the company's telecom customers reports paying $500,000 for 0.15-micron mask sets, and one customer in the computer industry has reported mask costs of $1 million for a 0.13-micron part. "It's doubling every process generation, based on what we've heard," Chaffin said.

In advancing its hardware to the 32-bit level, Triscend had to put more thought into software. While 8-bit controller systems tend to be programmed by a single person, 32-bit controllers require multiple groups, and hardware and software are usually handled separately, Chaffin said.

For that reason, Triscend expanded its FastChip development environment. The A7 devices will use third-party tools to handle debugging, applications development and other chores. The intent is to allow hardware, software and applications to be developed in parallel, thereby speeding up system development, Chaffin said.

"People just entering the area are going to be three years behind in the maturity of the software," he said.

F astChip will include a debug tool from Wind River (Alameda, Calif.) that allows developers to download code directly to the ARM7 and to peer into the processor while code is running. For its part, Embedded Performance (Milpitas, Calif.) has developed an emulation environment for the A7. In addition, the A7 will be able to use tools from the ARM Consortium.

Triscend developed the A7 family in conjunction with its foundry partner, Sharp Corp. Triscend will continue to work with United Microelectronics Corp., its initial foundry and first investor, Chaffin said.

The first A7 chip, the TA7S20, contains 2,048 configurable-logic cells and is available for sampling now. Three other chips, which will offer from 512 to 3,200 configurable-logic gates, are due to be released in the first three quarters of 2001. Prices for the A7 will start at $12.95 each in quantities of 10,000.