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Intel, Rambus mull overhaul for RDRAM
Intel, Rambus mull overhaul for RDRAM TOKYO — In an effort to cut the high manufacturing costs of Rambus DRAM, Intel, Rambus and memory vendors are discussing overhauling the RDRAM core. By reducing the number of banks inside the core, the companies expect to realize a smaller chip size, closer to SDRAM, and so boost yields. The so-called 4i initiative comes as Intel is on the verge of launching its next-generation PC processor. The Pentium 4 is expected to roll out at speeds of 1.4 GHz as early as October. But analysts said the fast chip could face a slow ramp because it is tied to still-costly Rambus memory. The down side of the Rambus overhaul plan is that the new RDRAMs will likely take a performance hit and will require a different memory controller design from that used in Intel chip sets and other systems that employ the current RDRAM. Under the 4i initiative, memory makers will reduce the number of memory banks that divide the core of an RDRAM from 32 to four, reducing the die penalty perhaps by half for 256-Mbit-generation devices. Under that scenario, the random access of RDRAM would likely degrade, although Rambus argues that such a memory architecture would retain its edge over standard or double-data-rate SDRAM. Samsung Electronics, for one, is reportedly preparing to come out with a four-bank RDRAM by the end of the year. NEC Corp., however, said it is still evaluating the proposal and is unsure whether slimming down the RDRAM will be worth the effort. As a way to minimize random-access conflicts, Rambus DRAMS are divided into 32 dependent banks — dependent because every set of two adjacent banks shares one sense amplifier. That was done as a concession to DRAM makers. "The advantage of the dependent bank is that DRAM companies can reduce the die size because the total number of sense amps is reduced," said Nori Naono, president of Rambus KK (Tokyo). "But the disadvantage is you cannot activ ate an adjacent bank, which means that during a memory access that is completely random, the probability of bank conflict and the time the controller is waiting for an RAS/CAS will increase." Using 32 banks ensured RDRAM would have faster random access than SDRAM but made the core memory array larger than for SDRAM, despite the use of shared amplifier circuitry. SDRAMs have one sense amplifier for every bank but use only four banks. Now Rambus, Intel and memory vendors are said to be discussing an RDRAM core that would be more akin to the four-independent-bank SDRAM, as the "4i" designation would seem to indicate. Naono would not confirm whether Rambus and its partners are indeed considering such a core architecture. But should an RDRAM with four independent banks ever exist, it would still have better random-access performance than SDRAM, he said. That's because with RDRAM, every chunk of data that comes across the 64-bit memory bus is stored in one bank. With SDRAM the data is spread acr oss multiple DRAMs, so the same amount of data occupies more banks and increases the chance of an access conflict. "Let's say there are four RDRAMs and one controller," Naono said. "Each RDRAM has four independent banks, for comparison's sake. The data is stored into a specific bank of a specific memory chip. To the controller, this is a 4 x 4 configuration, so there's a 6.25 percent chance of a bank conflict. "With SDRAM, one cluster of data is spread out among all the memory chips. In this case, if the transaction is completely random, the probability of a bank conflict is 25 percent. This is why Rambus architecture has a big advantage, even if it has the same number of banks." Compared with today's 32-bank RDRAMs, however, the random-access performance of a four-bank RDRAM would suffer. "We're using 32 dependent banks now, so roughly speaking that's 16 independent banks," Naono said. "In the case where four RDRAMs are connected to one controller, the total number of independent banks is 64, wh ich means if the memory transaction is completely random the probability of a conflict is 1.5 percent." The potential loss of random-access performance apparently has not stopped Samsung Electronics, the largest DRAM producer, from backing the 4i plan. At a recent Platform 2000 conference, a Samsung official described a 4i 256-Mbit RDRAM that should cut the die-size penalty down from 10 percent to 5 percent. Eventually, Samsung believes it can reduce the area penalty to a mere 1 percent at the 1-Gbyte density, according to Ron Leckie, an analyst with Infrastructure who wrote about Samsung's presentation in a recent report. According to the Infrastructure report, the Samsung-built 4i 256-Mbit RDRAM should be ready by year's end and will be ready for production for systems coming out in the second half of 2001. But because of the differences in the core architecture, it will not work with Intel's 820 or 840 chip sets. Naono of Rambus acknowledged that an RDRAM memory controller is dependent on the DRAM's bank configuration; that's why Rambus decided to select a single, 32-bank standard for RDRAM, he said. While RDRAMs have been beset by high manufacturing costs and chip set delays, the high-speed DRAMs have started to make a strong showing in workstations. It's in such high-end systems, where memory bandwidth is most crucial, that NEC Corp. hopes to win more RDRAM business. NEC recently started producing 288-Mbit RDRAMs, and it expects to increase production from 150,000 to 750,000 per month between September and December of this year. At that density, NEC is placing a heavy emphasis on RDRAM, putting it ahead of SDRAM for high-end-system makers, which usually snap up the latest-generation devices. While NEC is aware of the 4i initiative, the NEC spokesman said it's too early to reach any conclusions about the low-cost RDRAM proposal. He acknowledged that there is some initial skepticism about the 4i plan because the company has been trying to push RDRAM at the high end while focusing on 128-Mbit SDRAM for the mid- and low-range. At the same time, NEC's RDRAM yields have already surpassed 50 percent and are expected to improve as the company moves to 0.18-micron process rules — circumstances that may call into question the need for an architectural overhaul. "Basically this [is] an Intel initiative," said an NEC spokesman here. "We really don't know anything about the architecture. The aim is to reduce the cost for Rambus. [But] if you want to go for low cost, our strategy is to use SDRAM. The whole point of Rambus is to meet higher performance." Intel, however, has clearly stated its interest in driving down the cost of RDRAM so that memory prices don't stand in the way of bringing down costs for Pentium 4-based systems. The company has urged DRAM makers to boost RDRAM production to reduce production cost, a request that has largely gone unheeded as many memory vendors scramble to meet strengthening demand for more profitable SDRAMs. SDRAM volumes up "Demand for Rambus in the PC is decreasing, and that's the reason for the revision of capacity," a Toshiba spokeswoman said. "Also, we made our projection a little bit bigger than how it is actually going to be. We'll still have enough for Playstation." In a fallback plan triggered by low production and the high cost of RDRAM, Intel recently said it will support PC-133 SDRAMs for Pentium 4 systems, a move it had tried to avoid. Along with the manufacturing problems plaguing RDRAM, Intel's decision to support the next speed grade for SDRAM has been seen as a road block to RDRAMs' mainstream acceptance. The 4i initiative, however, may give RDRAMs another shot at the mid- to low-end systems. Intel was not available for comment for this report.
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