Aldec Granted New Patent on Automatic ASIC Prototyping

Henderson, Nevada, May 23, 2006 -- Aldec, Inc., a pioneer in mixed-language simulation, hardware accelerators and prototyping tools has been awarded a new patent for automatic conversion of ASIC designs into FPGA devices. The US Patent 7,003,746 - which also has coverage in Europe, Japan and China - was developed jointly by Dr. Stanley Hyduke, founder of Aldec, and Slawomir Grabowski, hardware division manager. The patent is based on automatic conversion of ASIC designs with multiple clock domains and numerous clock-related signals into FPGA clocks and signals, while preserving the original ASIC design functionality in the FPGA architecture. "With full automation of the clock conversion process, ASIC designers will finally be able to do away with the main source of prototyping errors," stated Dr. Stanley Hyduke, President of Aldec, Inc., adding, "Error-free ASIC prototypes will now be done in a fraction of the time it took before."

ASIC Clock Conversion

The patented clock conversion algorithm is based on converting ASIC designs with multiple clock domains into equivalent circuits clocked by a single clock line. Gated and divided clocks are converted without any restrictions or limitations. By principle, multiple ASIC clock domains are always successfully converted into the equivalent FPGA circuit. The resulting FPGA design with only one clock line is free from timing violations, which usually occur while signals are crossing the clock domains. Also, because the patented algorithm automatically generates a single, low-skew clock line, the newly created FPGA design is free of setup/hold violations and race conditions. Finally, the clock conversion algorithm supports latches; it eliminates latch-to-flip-flop, flip-flop-to-latch and latch-to-latch timing violations.

All FPGAs have a limited number of clock lines and do not work well with multiple clock circuits. Conversion to one clock line allows quick implementation of designs in FPGAs without concern about timing issues. The patented algorithm allows full automation of the design conversion process and the user does not need to enter any constraints or other information to run synthesis.

Timing Analysis

The clock conversion algorithm is useful for quick timing analysis of the original ASIC design. If the ASIC design outputs differ from the equivalent outputs of the converted FPGA design, then timing violations are present in the original ASIC. The ASIC timing violations can be traced by performing static or dynamic timing analysis of the signal lines that produced different waveform signals. Companies with time-critical ASIC product development schedules will particularly benefit from the new patented ASIC prototyping software product that will be announced in Q3 2006. 

About Aldec

Aldec, Inc., a 22-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software and hardware for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers' needs with its offices located around the globe. Continuous innovation, superior product quality and a total commitment to customer service comprise the foundation of Aldec's strategic objectives. Additional information about Aldec is available at http://www.aldec.com.