High yield achieved for the world's smallest level 6-transistor SRAM memory-cell area (0.494µm2) ; stabilization technique addresses variability of transistor characteristics.
Tokyo, June 15, 2006 −− At the 2006 Symposium on VLSI Circuits being held in Honolulu, Hawaii, Renesas Technology Corp. today announced the development of a technique that enables stable operation of an SRAM (Static Random Access Memory) produced with a 65nm (65-nanometer) manufacturing process. The new technique uses a straight-pattern-shape layout and read-assist and write-assist circuits to overcome SRAM instability due to the variations in transistor characteristics that are inherent in fine-feature process technology. In particular, it addresses important issues related to the threshold voltage (Vth) such as the borderline voltage at which a transistor is turned on or off.
Stable operation was verified by a 65nm test chip containing an 8Mbit, 6-transistor type SRAM with the world's smallest level memory cell area: 0.494µm2. The test data show that the design approach gives a high yield for a wide range of global Vth variability — more than double the yield compared with a case without it. Applications include embedded SRAM for microprocessors and system-on-a-chip (SoC) devices.
Technique uses new cell layout and read- and write-assist circuits
There are three aspects of the new stabilization technique. First, a memory cell layout with straight shapes suppresses variability. Second and third, two types of assist circuits are added to the SRAM array. A Read-assist circuit achieves compatibility between stability and high performance, and a Write-assist circuit improves write speed. They are needed because of problems associated with the move to finer LSI fabrication processes with smaller feature sizes.
Specifically, the increasing miniaturization causes greater variations in key transistor characteristics, especially the threshold voltage (Vth). Of particular concern is the local Vth variability. This random phenomenon is caused by fluctuations of the state of impurities in semiconductors that arise even in adjacent transistors of the same shape. It can destabilize the operation of an embedded SRAM, which in turn can result in erratic system operation or even system failure.
The new stabilization technique implements a process technology that allows the pattern shape of the chip layout to be made straight, with no partial dimension modification. The resulting pattern shape can be simplified and the transistors' finished dimensions made more consistent. This suppresses the variability of transistor characteristics, improves the symmetry of memory-cell electrical characteristics, and also improves stability.
The Read-assist circuit automatically controls word-line potential, lowering it for increased stability when Vth is low, and raising it for better speed performance when Vth is high. Compatibility is thus achieved between stability and high performance if the local Vth variability increases and the symmetry of electrical characteristics deteriorates.
The Write-assist circuit uses wiring capacitance to quickly lower the potential of the memory-cell power supply line during a write operation. The voltage drops by approximately 0.1V in only 0.3ns, improving the SRAM's write speed.
Renesas points out that the stabilization approach announced at this year's Symposium on VLSI Circuits addresses fundamental problems associated with process miniaturization. Therefore the company expects that the technique will help improve the manufacturing process of future SoC devices that use even finer semiconductor process nodes.
