|
||||||||||
Azul Systems Deploys Denali Memory Solutions in Second-Generation Compute Appliances
Databahn DDR2 Controllers Used in Vega 2 Processor, The World's First and Only 48 Core Chip Design
PALO ALTO, Calif., July 12, 2006 -- Denali today announced that Azul Systems, the pioneer of the first network attached processing solution, has successfully implemented Denali's Databahn™ DDR2 memory controller in its new Vega™ 2 processor chip. Designed by Azul and fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) in an advanced 90 nanometer (nm) process, the Azul Vega 2 is the world's first and only single-chip 64-bit processor which contains 48 cache-coherent processor cores. The 812-million transistor chip will act as the foundation for the company's upcoming second-generation line of compute appliances, designed to deliver compute and memory resources as a shared network service for transaction-intensive applications in enterprise computing environments. Chip designers at Azul Systems implemented Denali's Databahn memory controller intellectual property (IP) in the Vega 2 chip to control the external DDR2-SDRAM memory devices. Azul also used Denali's MMAV™ memory modeling product to simulate the interaction between the Vega 2 chip and the external DDR2 devices to ensure correct and optimal performance early in the design process before the chip was fabricated. "Vega 2 is a very high performance processor, and the memory system is a critical element of the architecture required to sustain the levels of performance we have been able to achieve," said Scott Sellers, chief operating officer and co-founder at Azul Systems. "We use a sophisticated design and verification flow for our chip development, and by working with Denali, we were able to deploy the memory controller IP, utilize their memory simulation environment, and ultimately meet our aggressive development targets with a high-quality product." "Azul is clearly pushing the cutting edge of design with their Vega 2 chip," added Brian Gardner, vice president of IP products for Denali. "Integrating 48 processor cores on a single chip is not a trivial task. Configurable DDR memory controller IP is no trivial task either. Being able to configure our Databahn memory controller IP to support a high-performance application like Azul's is a testament to the quality of our own IP design teams, and to the architecture of our IP configuration engine. We are very pleased with the success of Azul's chips, and we look forward to participating in more successful chip designs with them." About Databahn IP Products About Denali About Azul Systems
|
Home | Feedback | Register | Site Map |
All material on this site Copyright © 2017 Design And Reuse S.A. All rights reserved. |