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TSMC and ARM Collaboration Achieves Significant Power Reduction On 65nm Low-Power Test ChipPower-management techniques provide proven path to power savings SAN FRANCISCO, CA. AND CAMBRIDGE, UK – July 18, 2006 – Taiwan Semiconductor Manufacturing Company (TSE: 2330, NYSE: TSM) and ARM [(LSE: ARM); (Nasdaq: ARMHY)], today announced that a design collaboration between TSMC and ARM on a 65-nanometer (nm) low-power test chip resulted in dramatic reductions in both dynamic and leakage power. The two companies cited innovative low-power design techniques, which were key to successful results. The year-long collaboration resulted in a 65nm test chip based on the ARM926EJ-S ™ processor demonstrating advanced power management technologies. By applying dynamic voltage and frequency scaling techniques, the test chip provides the ability to operate at the lowest possible power level for each mode of operation. In this case, the ARM® test chip achieved a dynamic power reduction of over 50 percent. Significantly, even on this TSMC 65LP low leakage process, advanced power-gating technology further reduced standby leakage by a factor of 8 times. “Power efficiency is the most important challenge facing the semiconductor industry as mobile devices exploit advanced processes to deliver greater functionality and performance" said David Flynn, ARM Fellow. “ARM and TSMC are partnering on 65nm and 45nm technology development, and this project demonstrates the significant leakage and dynamic power reductions that we can achieve through close technical collaboration and implementation of fully functional silicon.” “One of TSMC’s key differentiators is our insistence on proving our services and those of our partners in silicon, before bringing them to the design community,” said Ed Wan, senior director of Design Services Product Marketing, TSMC. “Our collaboration with ARM demonstrates beyond doubt that advanced process technologies, combined with innovative design techniques, and process-targeted libraries, can achieve distinct and significant power savings, which is absolutely vital to companies on the technological leading edge.” The test chip incorporates low- power memory macros, level shifters, retention flip-flops, and isolation cells in the library, which is characterized for multiple voltages. Power Management Strategy
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