|
||||||||||
ARM Enhances Reference Methodologies With Library Views And Pre-Compiled RamsSoC designers Can Now Harden ARM Processor IP With Predictable First-Time Success CAMBRIDGE, UK - July. 24, 2006 - ARM today announced at DAC, San Francisco, Calif., that the ARM® Implementation Reference Methodology, first introduced in 2001, now includes ARM ‘front-end’ views for standard cell libraries and optimized pre-compiled RAMs, part of its Artisan® physical IP family. The ARM Implementation Reference Methodology has established itself as the proven solution for hardening all ARM synthesizable processors from the ARM7TDMI-S™ processor to the recently-announced Cortex™-R4 processor and provides a simple, deterministic and rapid route from design to silicon. The ARM standard cell libraries and memories are delivered with views for leading Electronic Design Automation (EDA) tools and are available for all leading foundries. The pre-compiled RAMs have been developed for high-speed, low-power performance to meet a wide range of applications in consumer, communications, networking and wireless markets. Users can then tune the solution to their own Power Performance Area (PPA) needs by tweaking the scripts and substituting in the final libraries and RAMs in a controlled way. “The addition of the ARM ‘front-end’ library views and compiled RAMs enables our Partners to configure a silicon-ready ARM processor straight out of the box,” said Keith Clarke, VP, Technical Marketing, ARM. “Our Partners now have a far more complete reference solution than previously available and will be able to more quickly create implementations with proven, repeatable, power performance and area target numbers, to achieve swift design closure and sign-off.” ARM has developed their Implementation Reference Methodologies in collaboration with industry-leading EDA Partners including; Cadence Design Systems Inc, Magma Design Automation Inc and Synopsys Inc. "More than five years ago, Synopsys and ARM pioneered Reference Methodologies (RM) for synthesizable ARM processors -- a practice that is now common throughout the industry -- with a focus on increasing designer productivity, design predictability and performance," said Rich Goldman, vice president of Strategic Market Development at Synopsys. "Integrating RMs with 130-nanometer and 90-nanometer ARM physical IP, including Power Management Kits (PMKs) for leakage management and multi-voltage ARM Intelligent Energy Manager (IEM) support, we are providing a more complete, proven path for predictably hardening the synthesizable ARM processors through the Galaxy Design Platform." Availability About ARM
|
Home | Feedback | Register | Site Map |
All material on this site Copyright © 2017 Design And Reuse S.A. All rights reserved. |