Lexra tips free simulator; Mentor rolls 8-bit MCU

Lexra tips free simulator; Mentor rolls 8-bit MCU
By Michael Santarini, EE Times
July 17, 2000 (10:46 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000717S0009

Core vendor Lexra has announced that it is making its instruction-accurate Instruction Set Simulator (ISS) for its DSP processor, the LX5280, available free of charge on its Web site.

Lexra said the offering will give system-on-chip designers an easy way to evaluate their software code on a processor intellectual property core. The downloadable package includes the instruction-accurate ISS for software code development and debug, a well-commented FIR filter with a C code outer loop and optimized assembly inner loop, scripts to execute the code on the instruction-accurate ISS, and supporting files and documentation.

To assist in evaluating the core, Lexra is also providing a seminar on its Web site describing the hardware architecture, instruction set and software development tools for the LX5280.

In addition to the instruction-accurate ISS, Lexra also provides a cycle-accurate ISS for in-depth code profiling. With the cycle-acc urate ISS, designers can evaluate the performance of the 5280 running actual program code.

The full evaluation of the tool suite, including the cycle-accurate ISS and the interfaces to the Green Hills Multi-2000 Integrated Development environment, can be mailed to the customer based on a request generated via Lexra's Web site. The ISS is available to customers who register on the Lexra Web site at www.lexra.com.

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Mentor Graphics Corp. (Wilsonville, Ore.) has announced the M8051E-Warp-a high-performance, user-programmable 8051-based 8-bit microcontroller with a built-in chip debug feature.

The M8051E-Warp uses on-chip instrumentation (OCI) technology developed in collaboration with First Silicon Solutions (Beaverton, Ore.) to provide a JTAG-based debug solution.

The OCI, working in concert with in-circuit emulation tools, enables engineers to run at-speed validation of a system-on-chip and application program. The company claim s that application developers can perform simultaneous application development and validation on a hardware platform based on multiple third-party IP. In addition, application developers gain comprehensive real-time control of the processor from a PC-based interface with access to step, trace, soft breakpoints, hardware triggers and read/write control of registers and memory.

The core has a frequency-scalable state machine, is silicon-proven at 120 MHz and uses 0.18-micron process technology. Mentor said it can surpass 50-Mips performance reliably, uses only two clocks per instruction cycle and achieves six times the performance of a standard 8051 core at the same power consumption while maintaining full functional compatibility with legacy devices.

Mentor ships the M8051E-Warp soft core with sample synthesis and scan insertion scripts, a functional test bench with over 99 percent coverage and complete product documentation. The M8051E-Warp soft core is available now. Visit www.mentor.com/inventra.