Lucent aims latest Orca FPGAs at networking apps

Lucent aims latest Orca FPGAs at networking apps
By Loring Wirbel, EE Times
July 3, 2000 (3:46 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000703S0042

BERKELEY HEIGHTS, N.J. — Lucent Microelectronics' fourth generation of Orca programmable logic takes a tight aim at networking applications, adding such specialized blocks as embedded memory and phase-locked loops. Lucent explicitly calls Orca Series 4 a "platform for delivering network intellectual property."

Three platforms will be offered in Series 4: a generic FPGA family, a system-chip that combines FPGAs and field-programmable standard cells and an embedded FPGA core that can be implemented in a larger ASIC.

Shakeel Peera, senior marketing manager for networking IP at Lucent Microelectronics, said Series 4 development began two years ago when FPGA system developers realized their next-generation product would have to be optimized for ATM/Sonet, Internet Protocol and wireless backbone apps.

The embedded RAM blocks can be used as FIFOs, multipliers or content-addressable memories without adding more control logic. For standard memory, the blocks can be configured as a single 512 x 18 memory, as dual-port RAMs with an arbitrary number of words, or as one large 1,024 x 18 block.

Each FPGA and hybrid device has eight PLLs. Six of the eight are general-purpose analog PLLs, while two are high-precision PLLs for Sonet or time-division multiplexed apps.

Virtually every form of low-voltage-swing logic in commercial production can be supported by the Series 4 pins, including low-voltage, transistor/transistor logic (LVTTL) and Gunning transceiver logic on single pins, or low-voltage differential signaling and low-voltage PECL on dual pins. A terminating resistor implemented on-chip on each port can be turned on or off at will to support advanced backplane designs.

The programmable I/O is designed to meet the Utopia 4 spec at 416 MHz. I/O pins also can be muxed and demuxed to meet dual-data-rate and quad-data-rate DRAM interfaces. To allow for an extremely fast edge clock routing structure, any I/O pin can be used as an edge clock input pin. One pin can drive both a fast edge clock and a global on-chip clock.

The devices provide a glueless interface to Motorola's PowerQuicc and PowerQuicc II processors and StarCore DSPs jointly developed by Lucent and Motorola. Other network processors require minimal glue logic to interface with Orca. The internal on-chip bus is compatible with the ARM AHB bus and can link the microprocessor interface with embedded RAM blocks, FPGA blocks and control and status registers.

Four main densities of FPGA will be offered, ranging from the OR4E2 with 397,000 system gates to the OR4E10 with 1.27 million system gates. All FPGAs and hybrid devices are implemented in Lucent's COM2 0.13-micron CMOS process. The OR4E2, OR3E4 and OR4E6 families use six layers of metal, while the OR4E10 adds a seventh metal layer.

The field-programmable standard-cell family, defined to date by the OR46 22 hybrid device, will have a new high-end star, the OR8850, which combines eight independent serializer/deserializer channels with either 200,000 FPGA gates in the 8850L or 600,000 FPGA gates in the 8850H. The 8850 family also offers three 8-bit RapidI/O blocks that were not present in the 4462.

Beta development software and preliminary data sheets will be available to customers this month. The first silicon samples of the OR4E6 and the OR8850 will be offered in the fourth quarter. The OR4E2 and OR4E4 will be sampled in January, with the high-end OR4E10 sampled next March.