Denali launches Databahn memory subsystem generator

For Release June 19, 2000
Press Contact: Lane Mason, (650) 325-7241 x37, lane@denalisoft.com

www.denalisoft.com
www.eMemory.com

DENALI LAUNCHES DATABAHN MEMORY SUBSYSTEM GENERATOR

DATABAHN AUTOMATICALLY GENERATES MEMORY CONTROLLER CORES FOR NEW DRAM TECHNOLOGIES

Palo Alto, CA--June 19, 2000--Denali Software (Denali), Inc., the leading memory subsystem design and verification company, today announced availability of Databahn, a new online tool for memory subsystem generation. Databahn generates synthesizable memory controller cores for the latest memory architectures, and automatically produces C- level verification support for the memory controller and associated memory components.

Databahn speeds SoC designs by automatically generating memory controller cores and the associated memory subsystem models for leading edge DRAM technologies. For the first time, designers can go online to select a set of memory components, specify a memory controller configuration, and then instantly receive synthesizable RTL code for the controller and C-level simulation models for the resulting memory subsystem.

"Memory subsystems are quickly becoming the major bottleneck in SoC designs," said Mark Gogolewski, COO and VP of Engineering at Denali. "There is a huge void in tool availability to help designers architect and implement high-performance memory subsystems. Our customers asked us for this product. "

Denali is currently targeting Databahn for leading-edge memory technologies such as SDRAM, FCRAM and DDR-SDRAM, with plans to add support for other technologies later.

"The increasing fragmentation of memory architectures makes it difficult for designers to take advantage of the latest advances in memory technology. Because of Denali's close relationships with memory vendors, we are in a unique position to deliver a high-quality memory subsystem solution for all emerging technologies," added Gogolewski.

C- subsystem generation
One unique feature of Databahn is its ability to automatically generate C models for high- level architectural analysis and verification. The same models are used for functional verification, where they are tightly integrated to all the leading EDA tools including: VHDL and Verilog simulators, testbench generators, hardware-software co-verification, and system-level design tools.

Flexible interface to system design and major SoC architectures
Users of Databahn are able to quickly create different memory subsystem configurations, and instantly evaluate trade-offs. Options like buffer sizes, arbitration schemes, or caching strategies, can be modified to meet the needs of each specific customer application.

"Memory subsystems are a key performance bottleneck for many SoCs," noted Denali President, Sanjay Srivastava. "It is imperative that designers have a path to quickly evaluate different memory subsystem architectures within the context of their overall design. The current market for fixed-core memory controllers does not support this process. Databahn fills this critical void in SoC IP infrastructure technologies."

Denali also provides integrated support for leading SoC busses. The initial release of Databahn currently supports the prevailing system busses such as IBM's CoreConnect^TM, ARM's Advanced Microcontroller Bus Architecture (AMBA^TM), MIPS's SoC architecture, and SiliconBackplane^TM from Sonics.

Delivery through eMemory.com
Databahn will be available on the Internet and tightly integrated with Denali's eMemory.com site. The eMemory.com site is the popular portal for memory related information. A memory consumer can search through the memory database and select the desired part, and then use a convenient menu to select various parameters for the memory subsystem and the interconnect architecture. The tool then generates the C model or the synthesizable HDL model for the memory subsystem.

What others are saying:
The availability of the new memory subsystem generator benefits a broad range of industry players outside the design community, including EDA vendors, SoC enablers, and the memory vendors themselves.

"The ability of the Denali's Databahn memory subsystem generator to support the AMBA on-chip interface provides developers of AMBA-based systems-on-chip with a single product that can address different types of memory. This, coupled with the ability to simulate performance and then produce the synthesized controller, is very powerful," says Chris Jones, SoC Product Marketing Manager, ARM.

"Creating accurate subsystem memory models is a time-consuming process that distracts designers from focusing on their core development tasks," said Dan Ganousis, Sr. VP of Marketing, Innoveda. "The introduction of Databahn presents a powerful solution with models based on an open architecture, allowing smooth integration to verification tools such as Innoveda's VCPU. The result is a complete system verification environment for our mutual customers. Innoveda is pleased to be working with Denali to provide system designers complete solutions for design verification."

"Having easy availability of memory subsystem generator tools is critical to make sure that our new architectures like FCRAM get integrated in customers designs," said Dr. Masao Taguchi, General Manager of Memory System LSI Division at Fujitsu. "We have a very successful history of working together with Denali on modeling technology and we are happy to see it extended for memory controllers for our memory technology. As a leading provider of DRAM technologies, we applaud Denali's effort to build memory controller generators."

"Seamless Co-Verification users have been using Denali models for years with considerable success," said Serg Leef, general manager, SoC Verification Business Unit for Mentor Graphics. "Supporting complex memory controller architectures in embedded designs ties in perfectly with Mentor's forthcoming platform-based SoC design and verification tools, allowing designers to evaluate design options quickly and efficiently!"

Said Rahul Razdan, VP of Front-End Products at Cadence, "Memory subsystems are an integral part of the overall SoC design. Cadence and Denali have numerous common customers who couple our leading edge simulation solutions, such as NC-Sim, with Denali's memory modeling solution to verify such subsystems. We are delighted to see Denali extend its capability to provide complementary generation tools to automate and ease the system-level design task. By working closely together, we can provide tightly integrated solutions to our customers."

"Partnering with Denali to support our customers' applications by combining the SiliconBackplane MicroNetwork IP with Databahn-generated memory subsystems provides a high-performance solution for SOC design," said Grant Pierce, president and CEO of Sonics. "The configurability of the Databahn Memory Subsystem Generator complements the application-specific configurability of the Sonics MicroNetwork in a 'plug and play' SOC design flow that delivers fast and efficient shared memory designs."

"As platform approaches become more common in SoC design, efficient access to different types of external memory becomes a key challenge," said Cary Ussery, President and CEO of Improv Systems. "We see Denali's Databahn approach as a critical next step in integrating memory controllers into an overall platform design approach."

"The lack of memory subsystem generation tools has been a major roadblock to system architects and SoC designers integrating new memory architectures," said Bob Pierce, Director of Emerging Memories at Infineon Technologies Corp. "As a leading provider of advanced DRAM technologies, we are working with Denali to ensure that our customers can rapidly integrate our latest innovations. Denali's Databahn tool is what the memory industry needs and system designers require for fast memory controller development."

Price and Availability
Databahn is available immediately at a base price of $150,000, which includes a one-year subscription for online memory controller specification and model support for the controller and associated memory components. Pricing for RTL generation depends upon the memory technology and number of memory components validated with the system.

About Denali
Denali Software, Inc. is the world's leading provider of solutions for memory subsystem design and integration. Denali's products are used to model, design, and verify memory subsystems for networking, consumer electronics, computer systems, telecommunications equipment, and other electronic systems. Over 150 companies use Denali's tools, technology and services to streamline the traditionally inefficient flow of integrating new memory technologies into complex system designs.

Denali Software, Inc. is headquartered at 644 Emerson Street, Suite 7, Palo Alto, Calif., 94301.
650 325-7241, FAX: 650 325-5724. More information on Denali's products and services is available at www.denalisoft.com
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Reader Service Contact information:
Denali Software, Inc., 644 Emerson St., Suite 7, Palo Alto, CA, 94301. 650 325-7241 x18,
FAX: 650 325-5724, www.denalisoft.com, Alissa Gogolewski, alissa@denalisoft.com.

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