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First Silicon Solutions (FS2) Announces Support For Cadence Incisive ESL Verification Products
Interoperability Accelerates System-level Hardware Debug and HW/SW Co-verification Solution for SoC Development
PORTLAND, OR, January 9, 2007 -- First Silicon Solutions, (FS2), a division of MIPS Technologies, Inc. (NASDAQ: MIPS) and a leader in on-chip instrumentation IP for high performance debug solutions, has announced support and interoperability with the new Incisive ® Electronic System Level (ESL) products from Cadence. The Incisive ESL solution addresses emulation, prototyping and silicon simulation applications to system-level verification. FS2 provides processor and systems level on-chip instrumentation, probes, and software to facilitate SoC functional controllability and observability at both the processor IP and system level interfaces. FS2 augments the Incisive capabilities by providing customers easier-to-use and more powerful hardware and software co-verification solutions to simplify and link functional and performance analysis between EDA and hardware-based debug tools. FS2 IP and probe solutions developed as part of the Cadence HW/SW co-verification ecosystem have been optimized to support cross probing, debug and analysis for system-level platform verification with Incisive Palladium ® and Xtreme ® series and Incisive Enterprise Simulators. This allows customers better, faster, and simpler interfaces between embedded hardware designs being verified and their supporting embedded software environments. "System Debug continues to be an increasingly important aspect in the verification flow, both at the platform prototyping and silicon production level. Tightly integrating tools for hardware and software verification with EDA capabilities and flows via on-chip instrumentation is critical for today's increasingly complex designs," said Rick Leatherman, vice president and general manager of FS2. "We are pleased to be working with Cadence in creating these vital connections between hardware instrumentation and software-based verification flows." One key innovation that will be supported in current releases of all FS2 tools is support for adaptive test clocks (RTCK) and low speed clocked for JTAG connections to Xtreme and Palladium systems. RTCK support allows transparent integration of the JTAG interfaces at lower core emulation speeds. This allows FS2 system probes tied to the emulation system to support higher speed JTAG interaction with a variety of software debuggers, ranging from 8-bit 8051 cores to leading-edge MIPS ® processors. "In the last few years, we have worked very closely with FS2 supporting our Xtreme and Palladium customers, helping them to cross debug hardware and software in their design and shorten their time-to-market." said Ran Avinun, Incisive marketing group director, Cadence. "The combination of FS2's debug capabilities and the new Cadence ESL Verification solution automates and manages the entire process from system definition to system validation, providing the most predictable path to system-level quality." FS2 and Cadence will enable interoperability between FS2's Logic Navigator TM and Bus Navigator TM on-chip instrumentation trace products and the Incisive ESL product solutions to allow high performance triggering and tracing of embedded IP blocks and embedded buses (AMBA, OCP, etc.) respectively. The integration between FS2 and Incisive allows users to analyze essential signals and enable trace capture using Navigator on-chip instrumentation flow with handoff via VCD and other standard formats to Cadence verification tools. All FS2 instrumentation products are supported by FS2's high-performance System Navigator TM probing technology and work in conjunction with FS2's embedded processor debug blocks to provide comprehensive on-chip instrumentation and debug solutions. About FS2
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