eASIC and ASIC Architect Partner to Deliver New High-Speed PCI Express and DDR2 Interfaces for Nextreme Structured ASICs

ASIC Architect join eASIC's growing eZ-IP Alliance

Santa Clara, California -- February 5, 2007 - eASIC Corporation, a provider of Structured ASIC devices and Configurable logic IP, and ASIC Architect, a leading supplier of high speed IP cores, today announced the immediate availability of two new high-speed interfaces for eASIC's 90nm Nextreme Structured ASIC Family: PCI Express (PCIe) Endpoint Controller and DDR2 memory controller. The PCIe controller features maximum data throughput with a latency of less than 11 clock cycles and provides local connectivity for, wireless, desktop, enterprise and communications system platforms. The DDR2 core is tuned to provide connectivity to the latest DDR2 memories at speeds up to 533MHz. Both PCI Express and DDR2 Controllers have been hardware proven in eASIC's Nextreme Structured ASICs devices.

As a new member of eASIC's eZ-IP Alliance, ASIC Architect will collaborate with eASIC to port its world-class high speed interface IP library to Nextreme Structured ASICs in order to provide system designers with the advantages of low unit-cost, no mask charges, and fast turnaround.

“Customers are always looking for cost-effective silicon-proven solutions without compromising on performance, latency and gate count,” said Purna Mohanty, Vice President of ASIC Architect, Inc. “Implementing the high-performance cores from ASIC Architect on Nextreme Structured ASICs provides proven platform for fastest time-to-market for our mutual customers”.

“ASIC Architect brings a wealth of experience in developing high performance interfaces for multiple applications,” said Jasbinder Bhoot, Senior Director of Marketing at eASIC Corporation. “In addition to broadening the eASIC IP portfolio, ASIC Architect contributes expertise and support to ensure customers get to market quickly. By partnering with leading IP providers, eASIC reinforces its goal to provide the electronic design community with an efficient alternative to existing FPGA and ASIC solutions through a disruptive technology”.

About The PCIe Endpoint Controller Core

The PCIe x4 Endpoint Controller Core is the first to be implemented on eASIC's Nextreme Structured ASICs. It is part of a portfolio of ASIC Architect PCIe options that are available in multiple application interface datapaths (32bit, 64bit, 128bit) and multiple lane configurations (x1, x2, x4, x8, x16). The application interface of these cores can be optionally integrated with AMBA® 3 AXI™ Bridge Core from ASIC Architect to connect to the AMBA 3 AXI bus.

About the DDR2 Memory Controller Core

The DDR2 Controller Core in 64bit configuration with ECC is the first to be implemented on eASIC's Nextreme Structured ASICs. The DDR2 Controller Core comes with configurable memory datapath widths (16bit, 32bit, 64bit) with optional ECC support. The architecture of the product defines a very low latency and high throughput of the core. The application interface of the core can be optionally integrated with AMBA 3 AXI Bridge Core from ASIC Architect to connect to the AMBA 3 AXI bus.

About ASIC Architect

ASIC Architect, Inc. is a high speed interface controller company based in Santa Clara, California and Bhubaneswar, India. . The company strives to provide high quality products, support and services to its clients world-wide and it's this focus that translates into high quality of our products and services. Currently, the company has products and services in PCI Express, DDR , SATA Controllers area. In addition to the main products, the company also provides peripheral cores for its main core products in order to accelerate chip-level integration and shorten time to market. ASIC Architect's products and services are targeted and tailored towards networking, storage, wireless and consumer product markets. http://www.asic-architectinc.com

About eASIC

eASIC is a fabless semiconductor company offering breakthrough Structured ASIC devices and Configurable Logic IP aimed at dramatically reducing the overall fabrication cost and time of customized semiconductor chips. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology of FPGA-like programmable logic coupled with ASIC-like Via-layer customizable routing. This innovative fabric efficiently employs mask-less customization with Direct-write e-Beam, and thus allows eASIC to offer NRE-free Structured ASICs.
Founded in 1999, eASIC Corporation is privately held, headquartered in Santa Clara, California. Investors include Vinod Khosla, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, and Evergreen Partners. www.eASIC.com