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Stream Processors, Inc. Announces Storm-1 Family of Data-Parallel Digital Signal ProcessorsNew Class of DSPs Removes Programming Barriers for Parallel Processors and Unleashes Industry-Leading Performance ISSCC 2007, SAN FRANCISCO – Feb. 12, 2007 – Stream Processors, Inc. (SPI), a fabless semiconductor company that is making parallel processing simple, today announced the first members of its Storm-1™ family of data-parallel digital signal processors (DSPs) – the SP16-G160 and the SP8-G80. Based on the company’s breakthrough SPI Stream Processor™ Architecture (detailed in a separate announcement issued today and titled “Stream Processors, Inc. Announces Breakthrough Digital Signal Processor Architecture at ISSCC 2007”), the Storm-1 family combines the ability to scale to 80 giga multiplications and accumulations per second (GMACs/s) performance with a simple, predictive and efficient C programming model. The Storm-1 family is suitable for a wide range of demanding signal processing applications, such as high-definition video H.264 HD encoding, transcoding, analytics, image processing and video surveillance with processing headroom for customer-specific enhancements. “Data bandwidth and ease of programming are what matter most in modern computer systems,” said Chip Stearns, president and CEO of SPI. “The level of performance offered by the Storm-1 family will enable a new wave of innovation in markets that have been begging for an easy-to-use path to higher performance without sacrificing software programmability.” The SP16-G160 and SP8-G80: A New Class of DSPs Each device includes a MIPS32® 4KEc® CPU core for system tasks, and a second MIPS32® 4KEc® that is dedicated to handling main DSP threads and making kernel function calls to the DPU for acceleration. A rich set of I/O includes Gigabit Ethernet, PCI, and high-speed data ports for video and communications. Designed to make parallel performance easily accessible to programmers, a key feature of the architecture is its compiler-managed memory hierarchy and single-threaded approach. A simple C programming model allows specification of compute-intensive kernel functions that process data records, enabling the compiler and hardware to efficiently manage on-chip memory and synchronize runtime direct-memory access (DMA). Kernel functions process stream data in a data-parallel fashion across all of the lanes. Unlike traditional DSPs, there is no need to spend time manually choreographing caches or dealing with synchronization of DMA, or load-balance cores, greatly increasing predictability and simplifying the overall programming task. The Storm-1 SP8-G80 device leverages the SPI Stream Processor Architecture in an eight lane flavor offering 80 GOPS of performance. Additional information about the Storm-1 family can be found at http://www.streamprocessors.com/ Development Tools The Storm-1 Development Kit supports evaluation and software development on SPI hardware, and has I/O options to support multiple video sources and formats, including HD and D1. Price and Availability About Stream Processors, Inc.
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