TSMC Achieves 65 Nanometer Embedded DRAM Milestone

Manufactures First Functional 65nm Embedded DRAM Device

Hsinchu, Taiwan – March 6, 2007 –Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today announced the foundry industry’s first functional 65nm embedded DRAM customer product. The product contains millions of DRAM bits and was silicon verified first time right.

The achievement of this milestone builds on TSMC’s 65nm leadership that began when the company became the first foundry to achieve 65nm product production in the second quarter last year. The company has also been in 90nm embedded DRAM production since the first quarter of 2006. There have been rich sets of memory macros, developed by TSMC’s design team, which are being used in more than a dozen of 90nm customer products.

TSMC’s 65nm embedded DRAM process and IP provide a higher bandwidth, lower power consumption, and a close to 50% smaller cell and macro size than previous high density memory generations.

"NVIDIA is pleased to have collaborated with TSMC on their new 65nm embedded DRAM process, which has proven to be an excellent platform for our latest handheld GPU product," said Michael Rayfield, general manager of the handheld division of NVIDIA Corporation. "The efficiencies of the embedded DRAM process allowed us to raise the bar for features found in mainstream cell phones."

“We’ve talked to customers and understand their needs. TSMC firmly believes that this new embedded DRAM process and IP are well suited for the demands created by the convergence of the wireless, consumer and communications devices. The results will be multi-functional computing platform that will spawn the next generation of innovation,” said Jason Chen, vice president of corporate development, TSMC.

The 65nm embedded DRAM’s higher bandwidth is ideal for game console, high-end networking, digital consumer, and multimedia processors. It consumes less active and stand-by power than alternative high density memory technology while eliminating the need to power up I/Os.

TSMC 65nm embedded DRAM’s flexibility supports product designs that feature a smaller form factor by enabling both logic and memory functions to be built on a single device thus saving board space and enhancing systems reliability.

TSMC 65nm embedded DRAM uses a low thermal budget module that can be added to the company’s standard CMOS process. It is compatible with all 65nm logic libraries making it an efficient process for IP reuse. The embedded DRAM design features improved retention time and special power saving options for low power applications including sleep mode, partial power cut-off and on-chip temperature compensation.

The 65nm embedded DRAM process is built on up to 10 metal layers using copper low-k interconnect and nickel silicide transistor interconnect. It features a cell size less than a quarter of its SRAM counterpart, and macro densities ranging from 4Mbits to 256Mbits.

Both the 65nm embedded DRAM and IP are supported by TSMC’s Design Support Ecosystem featuring DFM-compliant 65nm products and services; by TSMC’s Reference Flow 7.0 design methodology; and by a variety of process-proven TSMC and third party IP and libraries including SRAM compilers, I/Os and standard cell libraries.

About TSMC

TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company's total managed capacity in 2006 exceeded seven million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GigaFabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.