Solutions to CMOS scaling limits are appearing, conference hears

Solutions to CMOS scaling limits are appearing, conference hears
By David Lammers, EE Times
May 26, 2000 (8:58 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000526S0001

ORLANDO, Fla. ( ChipWire)-- With the end to CMOS scaling in sight, the semiconductor industry is broadening its targets and reemphasizing the analog design skills needed for communications, according to participants at this week's Custom Integrated Circuits Conference (CICC).

CMOS has a finite limit defined largely by how low voltages can go, and by the reliability of gate oxides at 15 angstroms (1.5 nanometers).

As those limits are approached and brute-force scaling becomes more costly, companies at CICC showed that they are ready to put more resources into new process technologies and system-on-chip design skills, including the mixed-signal technologies that are a forte of the conference.

For example, Seiko Epson Corp. showed a simple but ultralow-power device using silicon-on-insulator (SOI) technology. And a team from a Belgian university described a gigasample digital-to-analog (D/A) c onverter that could pave the way for more complex CMOS system chips.

The limits of CMOS and beyond were explored in a scheduled talk by Tak H. Ning, an IBM fellow working at the Thomas J. Watson Research Center in Yorktown Heights, N.Y. He said, "we can see the ceiling" to CMOS scaling, probably within the next decade as gate lengths of about 25 nanometers are achieved. While forecasts, made as recently as 1998, predicted that it would take 20 years to reach 25-nm gate lengths, accelerating technology in recent years may bring performance-driven companies to 25-nm CMOS capabilities by 2010, he said. "We are rushing toward the end point a little bit faster," he said.

Recalling the end of bipolar IC technology in mainframes due to high standby current, Ning said a similar end point will come for CMOS technology, though for different reasons. "Everything has a limit and the limit never changes," he said.

Ning said he does not think that the semiconductor industry will be able to move away from si licon dioxide as the gate insulator. "After many years of hard work, I have not seen one high-k gate insulator that I like," he said.

The "magic of silicon" comes from its good match with silicon dioxide as the insulator, and Ning said "we are asking for a miracle" if we expect high-k gate materials to have the same natural affinity.

Moreover, there are physical limits to how far the threshold voltage can be scaled. Citing a need to keep a 3:1 ratio between the operating and threshold voltages, Ning argued that a "natural limit" of about 0.3 V_th exists. At less than 1 volt, the V_thand the off-current of the device become uncomfortably close, making it hard to maintain an acceptable standby current.

Devices with a 25-nm gate length probably will operate at a V_dd of 1 V, particularly for high-performance devices.

"When you think about the power supply, the limit is approximately 1 volt. And at the rate we are approaching 1 volt, the end is in sight," Ning s aid.

Also, for flash memories, reducing the tunnel-oxide layer to 90 angstroms (9 nm) or below also will prove to be a limit. "For flash, there is no way around that limit," Ning said. He predicted that magnetoresistive RAMs and ferroelectric memories may displace flash as the dominant non-volatile technology.

CMOS technology won't be replaced just because it is nearing its limits. Rather, in the new millennium engineers will need to deal with those limits by coming up with increasingly creative technologies.

Ning recommended using a repertoire of tricks ranging from cooled CMOS to multichip packaging, as well as SOI and silicon germanium processes. The largest challenge will come from the need to combine analog and digital functions as well as embedded DRAM in system-on-chip ICs.

Ning said that even a moderate cooling of CMOS -- from the 100°C temperatures routinely seen in chips running in servers, down to room temperature or below -- can be worth the cost of a compact refrigeration uni t. Cooled CMOS can accept a 20 percent reduction in operating (V_dd) and threshold (V_th) voltages, delivering "as much improvement as the shift from aluminum to copper" interconnects.

Similarly, SOI technology also is worth the extra cost. Going from bulk silicon to SOI improved the performance of a PowerPC processor from 450 MHz to 550 MHz, he said, citing an IBM presentation at last February's International Solid State Circuits Conference (ISSCC).

For that kind of performance boost, "the extra $500 per [SOI] wafer is nothing," Ning said.

At the CICC, historical justice may have been served when a group from Seiko Epson - the Japanese company that pioneered the commercial use of CMOS technology for watch ICs - took the stage to espouse the power-saving capabilities of SOI technology.

Akihiko Ebina described a circuit that, admittedly, was low in density (1,200 gates) and relatively slow, running at the 32-kHz frequency of a quartz oscillator. But the power consumptio n of the SOI-based device was rated at only 13 nanowatts, which he said was one-fourth to one-sixth the power drawn by a conventional integrated circuit.

The chip developed at the Seiko Epson IC R&D center is intended for a watch that recycles its kinetic energy, an application that also has positive implications for other portable devices. Though Ebina did not describe the watch in detail, he indicated that its mechanical spring would drive the watch hands while simultaneously providing power to a quartz oscillator and controller chip in order to ensure "quartz-watch" accuracy. The watch might also have a solar cell.

In portable devices with such a design, the controller IC must run at 0.5 V or less and draw only 50 nanoamperes of current. Ebina said the extremely small junction capacitance and leakage in SOI devices, as well as advantages to the floating-body effect for low-power-consumption chips, drove the group to try SOI technology. The prototype IC draws an amazingly small amount of current while in the "off" state: only 0.1 picoampere per square (micrometer per unit of gate width) for each transistor. That supported a design that could use an operating voltage as low as 0.35 V.

As wireless technology grows in importance, more research groups are devoting efforts toward combining digital and analog circuitry on a CMOS substrate. A major challenge is the D/A and A/D converters that serve as interfaces between digital and analog circuits.

Ann Van den Bosch and Mark Borremans, both doctoral candidates at the Microelectronics and Systems Center (MICAS) at the Katholike University at Leuven, Belgium, introduced a CMOS D/A converter with 1-bit resolution that achieves Nyquist conversion at 1 gigasample per second.

The chip is believed to be the first D/A to achieve the gigasample performance level, said Tim Reuger, a member of the CICC technical program committee.

High-performance D/A converters are used in Global System for Mobile Communications phones, high-definition TVs and ot her applications. The Van den Bosch design was implemented in a 0.35-micron CMOS process, and achieves a 62 dB measured spurious-free dynamic range as it progresses from the off state to Nyquist conversion rates. The circuit area is only 0.35 mm², with power consumption rated at 110 milliwatts for a 490-MHz input signal at a sample frequency of 1 gigasample per second.

Custom-designed circuits and hand layouts are common in analog ICs, partly to minimize the die size. For the D/A converter, manual design and layout at the transistor level were used, Borremans said. Guard rings were used to avoid coupling between the digital and analog blocks. The digital portion also was handcrafted.

The pair did a manual extraction of the parasitics in order to optimize the design, and created new behavioral models by studying previous designs.

"Our work was influenced by the output impedance, and normally designers tend to only look at the static impedance. What we learned is that performance in f act depends on the frequency dependence. You have to take frequency dependence into account in order to take performance this far," Van den Bosch said.

The pair, who are husband and wife, worked under the direction of Willie Sansen and M. Steyaert at MICAS. Van den Bosch is a veteran in the D/A field, with a 14-bit D/A converter introduced at the 1999 ISSCC. She said several European semiconductor companies have approached Sansen about licensing the design for use in commercial ICs. The D/A converter will be further described at the upcoming International Symposium on Circuits and Systems in Geneva.