Tool converts hard IP to synthesizable models

Tool converts hard IP to synthesizable models
By Michael Santarini, EE Times
May 15, 2000 (8:13 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000512S0037

SAN JOSE, Calif. — Circuit Semantics Inc. has introduced an automatic functional extraction tool that lets designers convert hard intellectual property (IP) designs into gate-level Verilog models, which can then be transferred via logic synthesis tools into a new design.

The tool promises to speed IP repository building efforts exponentially. The downside is that it can be misused to reverse-engineer cores.

The DynaModel tool from Circuit Semantics generates fully functional Verilog simulation models abstracted from full-custom and hard intellectual property blocks to support the reuse of legacy IC layout in new designs, said Arnie Becker, the company's director of marketing.

Becker said DynaModel is targeted at systems and semiconductor houses with large libraries of legacy hard cores that want to reuse the code in nex t-generation designs.

"If you look at companies like STMicroelectronics, Motorola and Infineon, they would like to reuse legacy IP, place them in their repositories and have some way to migrate them," said Becker. "This will allow them to do that."

The tool is essentially a much higher-capacity version of Circuit Semantics' DynaCell and DynaCore characterization tools. Becker said the tool has thus far been used for 500,000-transistor design and blocks, and the company is not aware of a physical capacity limit. He said the tool in its current 32-bit configuration does require a large amount of memory. But the company is thinking of porting the tool to 64-bit, which would add speed and ease memory demands.

Different device

Becker said the tool is different from process migration tools in that the DynaModel produces a gate-level model, while process-migration tools convert physical design from one process geometry to another in the physical domain.

Engineers feed the tool a Spice ne tlist and a configuration file. DynaModel reads in the Spice netlist, partitions the block, and then extracts the function for each partition.

The tool then generates a gate-level functional model with unit delay timing support, a Verilog netlist as well as .lib and TLF files. A future release will embed timing in the model.

During the setup of DynaModel, Becker said, users identify the structures of all of the sequential elements to DynaModel and supply a Verilog mapping file that is used to represent that sequential element to the synthesis tool.

Becker said this mapping file can be a simple HDL description of the sequential element or it can be as complex as a gate-level netlist expressed in the technology into which that block will be mapped. He said if the mapping file is an HDL description, the resulting Verilog model generated by DynaCore becomes a technology-independent "Soft IP" model.

After extracting the functional model, engineers can use a logic synthesis tool to map the design into the new technology. Becker said Circuit Semantics realizes that the tool could also be misused to essentially reverse-engineer an IP vendor's hard core-that is, if that vendor provides customers with Spice source.

He said IP vendors are worried that people might misuse the tool so in the event someone wanted to use it illegally, Circuit Semantics encourages IP vendors to use encryption.

Feeding a full-custom design that was optimized for performance into an automated ASIC synthesis flow often results in a slower design. To combat that, Becker said, the company plans to announce a partnership with Prolific and Ultima technology to create a flow based on an optimized Spice netlist that will re-lay out a design to maintain full custom performance.

Becker said designers can also use DynaModel to convert transistor-level design into a gate-level model that can be simulated using a faster gate-level simulator.

DynaModel is available immediately running on Sun and HP workstations. The list p rice is $95,000.