Inovys Introduces YieldVision(TM), a Revolutionary Suite of Analysis Tools for Advanced SOCs

Toolset Enables Accelerated Yield Ramps by Closing the Loop Between Test and Fab

PLEASANTON, CA-- July 10, 2007 - Inovys Corporation, an innovative provider of yield, failure analysis and test solutions for the semiconductor industry, announced today the launch of YieldVision, a unique integrated suite of tools that enable real-time statistical analysis of electrical failures on product die. YieldVision provides customers with the ability to efficiently triage, or reduce, large quantities of electrical failures into specific logical faults, which results in fast localization of the root cause physical defects. By seamlessly linking electrical test with physical layout data, YieldVision enables customers to effectively identify invisible yield loss mechanisms in complex logic circuitry, accelerating the new product introduction phase of their most advanced devices.

Inovys has a heritage of providing advanced Design For Test tools to leading SOC semiconductor companies. YieldVision extends this by linking test back into the fab through logic bit maps for electrical faults. Stuck-at faults and timing faults in scan chains, logic and clock trees, may be found more efficiently than with current methods. YieldVision efficiently captures the full structural and performance data across the die on a wafer in a single pass using a high bandwidth data collection engine. This data may be stacked and analyzed by die, wafer, lot, or multiple lots of wafers -- enabling the traditional failure analysis process to move from a singular to statistical approach. YieldVision triages the gigabytes of electrical failure data into manageable kilobytes of logical fault data by applying proprietary "structural DNA" decoding algorithms. Physical bounding boxes, or Splats™, are produced to localize each fault to a small area on the die which may be diagnosed to find the contributing defect. Splats have the additional benefit of providing a secure method for protecting IP when sharing layout information with foundries. This enables product groups to more efficiently collaborate with their foundry, whether in-house or outsourced, on defect diagnosis -- reducing this process from weeks to hours. YieldVision provides high accuracy for the lab while also providing high throughput for production -- critical for both new product introduction and ongoing electrical line monitoring.

"Inovys is well known for our award-winning innovative software analysis tools," said Colin Ritchie, vice president of marketing, Inovys Corporation. "YieldVision builds on a foundation of more than fifty man-years of software IP investment and now takes it to a new level, finally providing customers the ability to close the loop between test and fab."

"I am very pleased to see Inovys deliver the first of many new products that help enhance customers' yield analysis capabilities," added Dave Bakker, executive chairman, Inovys Corporation. "YieldVision has already been successfully deployed by our targeted early adoption customers, helping them identify critical yield limiting defects that had been escaping detection, until now."

You can see YieldVision at SEMICON West at Moscone Center in San Francisco, CA, July 17-19, 2007 in booth T12 - West Hall. To schedule a demo, please send your request to demo@inovys.com.

About Inovys Corporation

Inovys provides innovative yield enhancement, failure analysis, and design debug solutions for the semiconductor industry. Inovys customers include the industry leading Integrated Device Manufacturers (IDMs), Fabless companies, Foundry and Test subcontractors. These companies use Inovys solutions to accelerate their new product introductions and optimize yield ramps of their advanced system on chip (SOC) devices. The revolutionary Inovys Design For Test (DFT) analysis toolset enables customers to reduce electrical failure resolution cycle times from weeks to hours. Learn more about Inovys at www.inovys.com