Lightspeed Logic announces Manufacturability-Optimized Reconfigurable Logic IP for 65nm and 45nm

New Logic IP reduces lithography and stress-related variability as well as modeling guardbands, enhancing yield to surpass standard cell equivalent density

Santa Clara, CA—July 18, 2007—Lightspeed Logic, the leading provider of mask reconfigurable IP, today announced a new generation of Lightspeed Logic’s Reconfigurable Logic IP for the 65nm and 45nm process nodes. In addition to providing increased flexibility in chip architecture, significant reduction in design cost and rapid time-to-market, the new Manufacturability-Optimized Reconfigurable Logic brings significant benefits to customers designing in advanced geometries. Because of the regularity provided by the tiling structure and the full knowledge of the immediate neighborhood of the tile, Lightspeed Logic, in partnership with its customers, can fully deploy OPC/RET technologies without facing the typical computing limitations associated with standard cell structures. As a result both lithography-related variability and stress-related variability are substantially reduced and the timing modeling does not need to accommodate overly pessimistic guardbanding.

Customers deploying Lightspeed Logic’s new Manufacturability-Optimized Logic can isolate the front-end and physical design engineers from the complex post-GDS manipulations and prevent the iterations between manufacturing and design typically experienced in advanced geometries. The Manufacturability-Optimized Logic also enables faster process debug and ramp up and delivers higher yields after the process has been stabilized. The addition of these new capabilities to the already high-density achieved by Lightspeed Logic’s Reconfigurable Logic IP will produce a higher number of known-good dies per wafer and effectively outperform the equivalent density of standard cells.

Lightspeed Logic has been collaborating with the industry’s leading DFM solutions provider, Clear Shape Technologies to model the manufacturability of the optimized tiles to achieve the goals described above. “Lightspeed Logic’s approach, combined with our recognized expertise and manufacturing models validated by the leading IDMs and foundries, is providing our customers with an appealing alternative to master the challenges of 65nm and below” said Atul Sharan, President and CEO of Clear Shape. “Our collaboration brings a unique advantage to designers in addressing nanometer scale semiconductor manufacturing challenges.”

“At 65nm and 45nm, Lightspeed Logic’s manufacturability optimized reconfigurable logic delivers a yield breakthrough, with yielded die surpassing that of traditional standard cell methodology” said Dave Holt, CEO of Lightspeed Logic. “This combined with increased performance and the increased flexibility in chip architecture, significant reduction in design cost, and rapid time-to-market, are a part of the innovation engine allowing the semiconductor industry to continue to keep pace with Moore’s Law”.

About Lightspeed Logic

Lightspeed Logic is a provider of mask reconfigurable intellectual property (IP), a digital logic implementation technology that provides time-to-market, yield, manufacturability, and development expense advantages over standard-cell implementation. Founded in 1996, Lightspeed Logic has developed and brought to market four mask-reconfigurable architectures, the most recent of which is a regular logic structure available for multiple foundries, IDMs and process nodes. The company is currently working with customers at the 150, 90, 65, and 45 nm process nodes. You can find more information on Lightspeed Logic at www.lightspeed.com