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Verisity donates temporal language to Open Verilog International Jennifer Bilsey VERISITY DONATES TEMPORAL LANGUAGE TO OPEN VERILOG INTERNATIONAL Temporal e Streamlines Interoperability MOUNTAIN VIEW, C-A May 1, 2000-Verisity Ltd., the leading provider of functional verification automation, today announced that it has donated the temporal subset of its e verification language to Open Verilog International (OVI). As e is the defacto standard for functional verification automation, the donation is significant because it will provide the industry with a proven, mature format for standardization. The subset will be given to the Formal Verification Technical Subcommittee for consideration as the standard property language for formal model checking. In a simulation environment, the temporal subset of the e language is used primarily to implement checkers. In a model checking environment, temporal e is ideal for representing properties to be verified. As the model checking market grows-more users adopt the technology and more vendors offer their own solutions-the need for a standardized language increases. The Formal Verification Technical Subcommittee's goal is to create a property language standard to make it easier for engineers to incorporate model checking into their existing environments. ``Since model checking and simulation must co-exist in a single verification methodology, having a single source to drive both engines streamlines interoperability," said Dr. Vassilios Gerousis, chairman of OVI's Technical Coordinating Committee. ``The potential of model checking technology for verifying complex IC and system-on-chip designs is very exciting, but the tools available today are perceived to be too hard to use and the languages are proprietary and very complex. Verisity's e language has all the right technical capabilities, and can be used to drive both simulation and model checking." ``OVI has a long and successful track record for driving standards that are beneficial to users," said Moshe Gavrielov, chief executive officer for Verisity. ``We are committed to establishing e as a standard and this donation is a significant step in our standardization roadmap." The Road to Standardization Traditional design languages--such as Verilog and VHDL--were created for hardware design and are not well suited for verification of today's complex integrated circuit, system-on-chip and system designs. C and C++ have emerged as alternatives, but are also not ideal since they were created for software design and lack sufficient hardware constructs as well as verification constructs. Verisity created the e language specifically for verification automation. The market has made it the de facto standard, thereby making it the obvious choice for standardization. Verisity's efforts towards standardizing e has thus far been focused on meeting the criteria to become a successful industry standard. Verisity believes that making e a successful standard includes all of the following criteria:
Verisity Ltd. develops, markets, and supports functional verification automation solutions for engineers to validate complex communications and other electronic systems. The company's products automate traditionally manual processes and have enabled customers to cut verification schedules by up to two thirds, shaving months off total project schedules. Verisity is the market leader with over 77 percent market share. The company is headquartered in Rosh-Ha'ain, Israel and has its main sales and marketing office in Mountain View, CA. Verisity's research facilities are also located Israel and California. The company currently employs over 120 people. For more information, see Verisity's web site at www.verisity.com. #### Verisity is a registered trademark of Verisity. All other trademarks are the property of their respective holders. |
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