Magma Unveils Talus ATPG and Talus ATPG-X – Expands Design-for-Test Capabilities with Physically Aware ATPG and On-Chip Compression

Advanced ATPG products support simultaneous analysis of multiple fault models, leverage multi-threading and on-chip compression to improve quality and reduce turnaround time and costs of nanometer ICs

SAN JOSE, Calif. -- Oct. 15, 2007 -- Magma Design Automation Inc., a provider of chip design software, today unveiled Talus® ATPG and Talus ATPG-X with on-chip compression. These advanced automatic test pattern generation (ATPG) products enable designers to significantly improve test quality, reduce turnaround time and cut costs of nanometer (nm) ICs. By integrating Talus ATPG and Talus ATPG-X into the Talus physical design environment, Magma offers the only IC implementation flow that provides true physically aware DFT.

The increased complexity and smaller feature sizes of today’s chip designs make it more complicated to test manufactured ICs. New failure mechanisms are constantly emerging. Traditionally, most defects could be detected using stuck-at patterns generated by the ATPG tool using just a simple gate-level representation of the design. To maintain required defect per million (DPM) rates today, IC manufacturers must use test techniques that detect timing, layout and power-related defects. As a result, quality testing now requires the use of more fault models and time-consuming and error-prone importation of data from various design tools. Traditional ATPG tools have neither the performance nor the capacity to deliver the required level of test quality and turnaround time for nanometer ICs.

Designed to concurrently target multiple fault models, Talus ATPG allows designers to improve test quality and turnaround time. It is fully integrated into Magma’s Talus IC implementation system and leverages the unified data model architecture to efficiently access timing, layout, power and other design data that is not available to other ATPG tools. This enables Talus ATPG to generate test patterns that other tools cannot. For example, Talus ATPG can generate tests for subtle bridge defects and crosstalk. Access to the unifed data model also allows Talus ATPG to support virtually all current fault-models and scale easily to support future models, and provides enhanced ease of use.

Talus ATPG includes additional capabilities that further reduce test time and test costs without reducing test quality. It is the only multi-threaded ATPG tool available, enabling it to provide higher throughput than conventional tools. Talus ATPG-X includes on-chip compression, offering a 40X reduction in test data volume. Talus ATPG also accurately diagnoses tester failures to find the logic and physical location of the defect. Diagnostic results can be passed on to Magma’s Knights Camelot™ and LogicMap™ products for correlation and failure analysis with the physical and electrical defects uploaded from the Magma Knights YieldManager® product.

"As designs move to smaller geometries, we must handle new, complex defect mechanisms. Generating test patterns with traditional ATPG tools becomes more complicated and time consuming," said Camille Kokozaki, director, Design Automation Services of IDT. "We find Magma's seamless flow and tight integration of ATPG, timing and physical layout to be very compelling."

"As a recognized innovator in communications technology, we are always looking for technologies to help us be first to market," said Jeff Hannon, vice president of Engineering at Comtech AHA Corporation. "With Talus ATPG’s multi-threaded engine, pattern optimization techniques, and ability to target multiple fault models in parallel we can generate more effective test patterns faster, helping us reduce turnaround time and costs on our advanced ICs."

"With the increasing cost to design and manufacture ICs, making the test process more efficient is critical – if you can’t test it, don’t build it," said Kam Kittrell, general manager of Magma’s Design Implementation Business Unit. "The addition of Talus ATPG greater strengthens the Talus platform’s test capabilities, allowing our customers to have higher confidence in their ability to build, test and profit from their IC designs."

Magma Highlights Talus ATPG and Inovys Interoperability at ITC

Magma will be highlighting Talus ATPG and Talus ATPG-X at the International Test Conference Oct. 23-25 in Santa Clara. Demonstrations of the new products as well as the interoperability with the Inovys Ocelot test systems will be available in booth 320.

Magma is also sponsoring a luncheon at ITC, Oct. 23 at 11 a.m. featuring Dr. Mohammad Tehranipoor assistant professor in the Electrical and Computer Engineering Department at the University of Connecticut. Dr. Tehranipoor will discuss the need to bring layout, timing and variation information into DFT/ATPG. To register for this event, please visit www.magma-da.com/ITC

Talus ATPG and Talus ATPG-X are currently available. Please contact Magma for more product details.

About Magma

Magma's software for designing integrated circuits (ICs) is used to create complex, high-performance chips required in cellular telephones, electronic games, WiFi, MP3 players, DVD/digital video, networking, automotive electronics and other electronic applications. Magma's EDA software for IC implementation, analysis, physical verification, circuit simulation and characterization is recognized as embodying the best in semiconductor technology, enabling the world's top chip companies to "Design Ahead of the Curve"™ while reducing design time and costs. Magma is headquartered in San Jose, Calif., with offices around the world. Magma's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at www.magma-da.com.