Toshiba Delivers DFI-Compatible DDR PHY to Speed Custom SoC Memory System Designs

New PHY Interoperates with Denali DDR Controller for Reduced Development Costs and Accelerated Time-to-Market

PALO ALTO, Calif. -- Nov. 13, 2007 -- Denali Software, Inc., today announced the availability of DDR PHY interface designs from Toshiba(R) Corporation that are compatible with the recently announced DDR-PHY Interface (DFI) version 1.0 specification. The DFI specification, originally developed by a group of semiconductor, IP and EDA companies including ARM(R), Denali(R), Intel(R), Rambus(R), Samsung(R) and Synopsys(R), defines a common interface between the DDR memory controller logic and the DDR PHY interface in order to minimize cost and accelerate time-to-market for DDR DRAM memory system development. Toshiba's custom SoC customers now have access to DDR PHY designs, in 90-nm process technologies and below, that integrate seamlessly to other DFI compatible designs, including Denali's Databahn(TM) DDR controller products.

"As a leading Custom SoC supplier, we are very happy to give our end customers the industry-standard DRAM PHY Interface (DFI), allowing customers the choice of buying or building their own memory controller," remarks Takashi Yoshimori, technology executive, SoC-Design of Toshiba's Semiconductor Company. "We have completed DFI testing using the high-quality Denali Databahn DDR1/2 controller, so interoperability with Denali is verified."

Toshiba's DDR2 Flexible PHY provides optimum balance between performance and flexibility. The unique partitioning facilitates optimization without loss of performance enabling customers to achieve a cost-competitive solution tailored for the specific application needs. "The effort, cost, and time to design and close timing on high-speed, DDR memory subsystems is geometrically increasing with the memory speeds," stated Brian Gardner, vice president of IP products at Denali Software. "This is becoming a universal problem because DDR DRAM memory is being used in virtually all electronic system designs, from cell phones and set-top boxes, to computers and network routers. The DFI specification provides a clean boundary between the Denali DDR1/2 memory controller family and the Toshiba DDR Physical Interface. Toshiba's end customers may use Denali's controllers for a broad set of applications, and be assured of easy integration and interoperability."

About the DDR-PHY Interface (DFI) Specification

The DFI specification was developed by expert contributors from recognized leaders in the semiconductor, IP, and electronic design automation (EDA) industries. The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with the goal of reducing costs for integrating DRR memory controller logic and DDR PHY interface while increasing performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. This enables reducing design and verification cost and time-to- market while increasing the potential for reusing the individual components that compose the memory system. The DFI Specification Rev is available online at http://www.ddr-phy.org.

About Denali Software

Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to- market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.