Applied plans five wafer-processing modules with guaranteed results

Applied plans five wafer-processing modules with guaranteed results
By J. Robert Lineback, Semiconductor Business News
April 5, 2000 (9:54 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000405S0002

MUNICH -- In a move to deliver more process technology with its equipment, Applied Materials Inc. this year plans to introduce five process modules that bundle together various tools, processes, and diagnostics capabilities for guaranteed results in the wafer fab. The first guaranteed process module will be announced in June, hinted Applied Materials managers during a press conference here at the Semicon Europa trade show.

"Our strategy is still to sell the best individual tools, but we spent a good part of last year restructuring the company in order to do an efficient job with these process module products," said James C. Morgan, chairman and chief executive officer of Santa Clara, Calif.-based Applied. "So, in the last six months we have seen a huge elevation of our thinking about how to do total solutions [by implementing these process modules]."

Applied's first five guaranteed process modules will be cover: transistor gate stacks, capacitor s, copper wiring, dual-damascene interconnects with dielectrics, and shallow-trench isolation.

As an example, Applied managers showed a slide of the copper-wiring processing module, which bundles the company's Endura tool for barrier and seed deposition, the Electra electrochemical plating system for copper filling of lines and vias, and the Mirra dry-in/dry-out chemical mechanical planaraization (CMP) platform with integrated cleaning. This module is completely integrated with processes, systems, metrology, and diagnostics, said David N.K. Wang, senior vice president and a member of the Office of the President at Applied.

When a chip maker buys one of the process modules, it will receive guarantees from Applied on the results on 200-mm wafers, including electrical performance, thickness of films, defect levels and throughput. Applied is tightly matching the throughput of all the tools inside the module to ensure there are no system bottlenecks. "A wafer in [the module] will result in a guaranteed wa fer out," Wang said.

A key target of Applied's process module strategy is to significantly reduce the time it takes to deliver new equipment while enabling semiconductor manufacturers to quickly ramp wafers in volume production. "Today you need capacity, productivity and now the shortest time to the market," Wang said during the press conference on Tuesday.

As an example, Wang said it took Intel Corp. 10 quarters (30 months) to put 0.35-micron technology into volume production during the 1990s. Several years ago, Intel reduced the time it took to move 0.25-micron technology into volume production to five-and-a-half quarters (about 17 months), he said. Intel further cut the time-to-ramp to four quarters (one year) in the 0.18-micron process generation, Wang added.

In order to help chip makers speed the launch of new technologies and device structures--such as copper interconnects and next-generation shallow-trench isolation--Applied believes tightly integrated process modules and tools will ease t he hurdles. "[Shorter] time-to-market cannot be easily achieved if you do not shorten the cycle time of development and then shorten the time of transfer and ramp into mass production," Wang urged.

Applied CEO Morgan added, "The integration of process diagnostics and control in the module [along with] information control system and optimization of the processes will give us a better product as modules than you get even as individual tool products."