Lattice Announces Production Release of Entire 90nm LatticeECP2M FPGA Family

Ground Breaking "Product of the Year" FPGA Family has Established a New Price/Performance Standard for Low Cost, High Volume FPGAs

HILLSBORO, OR - DECEMBER 17, 2007 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that all five of its LatticeECP2M™ FPGA devices, ranging in density from 20K LUTS to 95K LUTS, have been qualified and released to volume production. Announced in late 2006 and developed on advanced 90nm CMOS technology utilizing 300mm wafers, the LatticeECP2M devices are the industry’s first low cost FPGAs to offer high-speed embedded SERDES I/O, plus a pre-engineered Physical Coding Sublayer (PCS) block.

Previously, high-speed embedded SERDES serial I/O with speeds over 3Gbps had been available only on relatively expensive high-end FPGAs. Integrating this capability into a low cost FPGA fabric has made this higher performance interface technology accessible to a much broader range of applications in rapidly emerging, cost-conscious markets such as high volume communications, consumer, automotive, video and industrial equipment. The LatticeECP2M FPGA family has effectively bridged the price/performance gap between low cost and high-end FPGAs, and was named 2006 “Product of the Year” by Electronic Products magazine.

The LatticeECP2M devices also have dramatically increased on-chip memory capacity to support higher bandwidth, SERDES-based applications. LatticeECP2M Embedded Block RAM capacity ranges from 1.2 Mbit up to 5.3 Mbits, representing up to a 400% increase over competitive low cost architectures. The LatticeECP2M FPGA family offers a comprehensive array of features that includes 375 MHz block level performance, 18x18 multipliers, embedded memory, pre-engineered 533 Mbps DDR2 memory interface support, high throughput SPI4.2 support, configuration bitstream encryption and dual-boot configuration support. With the addition of 4 to 16 channels of 3.125 Gbps SERDES, the LatticeECP2M FPGAs are an innovative response to the broad range of customers who have been clamoring for low cost SERDES capability for PCI Express and Ethernet-based chip-to-chip and small form factor backplane applications.

“With its embedded high density RAM and DSP blocks, the LatticeECP2M FPGA provides versatile capabilities for image processing. Its pre-engineered source synchronous I/O facilitates implementing DDR2 and high speed LVDS interfaces that broaden the applications for our high-performance industrial digital camera and LCD monitor products. We believe these and other features of the LatticeECP2M FPGA are a key to successful product development,” said Michio Suzuki, Specialist, Product Development & Design Engineering Section, Toshiba Teli Corporation.

“Over the past year, all five device members in the LatticeECP2M family have moved from initial announcement to full volume production. Our commitment is to deliver tangible product innovation that brings heightened value to our customers,” said Stan Kopec, Lattice corporate vice president of marketing. “The LatticeECP2M family has redefined what a low cost FPGA should be, and has changed how FPGAs are evaluated for high volume applications. Reaching volume production so quickly is another example of how Lattice consistently delivers ‘More of the Best’ to its customers.”

Cost Optimized SERDES Architecture Provides Rich Feature Set

The SERDES integrated into the LatticeECP2M family has been engineered specifically for implementation in a cost effective, power efficient (power consumption as low as 100mW) quad-based architecture with 1 to 4 quads, depending on the size of the device. Each quad features 4 SERDES channels (4 complete TX and RX channels) and supports data rates from 270 Mbps to 3.125 Gbps. A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine and rate matching circuitry also are built onto the chip. The SERDES/PCS combination is designed to support today’s most common packet-based protocols, including PCI Express, Gigabit Ethernet, Serial RapidIO and wireless interface standards (OBSAI and CPRI).

The combination of SERDES, high performance DSP and a low cost FPGA fabric is extremely attractive to Edge and Access system vendors that are integrating these serial protocols into their wireless base stations, radio network controllers, DSLAMs and other last mile aggregation equipment that enable “triple play” technologies. Mass storage, high-speed server, medical imaging and industrial equipment system designers interested in low cost signal processing also will benefit from the LatticeECP2M family’s unique combination of features.

Design Tools and Intellectual Property Support

Design support for the LatticeECP2M devices is provided by the latest version of Lattice’s ispLEVER® design tool suite, Version 7.0 with Service Pack 1. The ispLEVER design tools provide access, in one software package, to all Lattice digital devices and include simulation and synthesis support from Mentor Graphics and Synplicity.

Customers also have easy access to a wealth of Intellectual Property modules through the IPexpress™ design flow. IPexpress-supported functions include PCI Express, SGMII, DDR1 and DDR2 memory controllers and SPI4.2.

About Lattice Semiconductor

Lattice Semiconductor Corporation provides the industry's broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays ( FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products.

Lattice continues to deliver "More of the Best" to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile, and low-cost FPGAs.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. For more information, visit http://www.latticesemi.com