Frontier refines C-based synthesis tool

A/RT Designer is based on the capabilities of the Archi tectural Synthesis Toolkit demonstrated by Frontier at the Design Automation Conference last May. The tool kit was introduced as an addition to the company's A/RT Builder translation tool that converts RTL structures described in C into Verilog or VHDL.

Herman Beke, chief executive officer of Frontier, explained that the Architectural Synthesis Toolkit started from a behavioral description in C and output ANSI C at the RTL level, which was then translated from C to VHDL or Verilog by A/RT Builder.

Noting that Frontier has now stopped offering the $45,000 Architectural Synthesis Toolkit, Beke added: "We decided this was not the right mix. Instead, A/RT Designer allows a designer to go from algorithmic C, or software C, all the way to VHDL or Verilog. We have also made a number of enhancements."

Beke added that, in the future, the tool would also be able to output C descriptions consistent with the Open SystemC definition when it is finalized .

"This [A/RT Designer] is a much cleaner approach, and the tools are much more user-oriented. There are automated processes within the tool, but they are based on user inputs. We don't force the designer to be a synthesis expert," said Beke.

Like the Architectural Synthesis Toolkit, A/RT Designer gives systems designers the ability to play graphically with resources, ALUs, multipliers, ROM, RAM and so on, to trade off the clock frequency, power consumption and die area prior to producing an RTL hardware description that can be exported to conventional logic synthesis.

Three-phase match

Beke said A/RT Designer is a good match to three phases of design commonly used by industry for complex ICs: C-language software-only design, real-time prototyping on an emulator or prototyping board, and the final system-chip design that has to be optimized for cost and power.

In current practice, Beke said, design teams often use different languages and EDA tools in the three phases, resultin g in a lot of verification work and error-prone rewriting of code.

In contrast, A/RT Designer can be employed throughout the steps between algorithmic C-code running on a workstation processor through to the generation of an optimized hardware description language implementation. Besides speeding the design process and avoiding costly recoding errors, the company said that the ability to explore and optimize at the C level dramatically improves power and area efficiency.

In addition to producing the variety of configurable data-path resources needed to implement original C code, A/RT Designer synthesizes the finite state machine or microcoded controller architecture needed to control the data path.

Use of A/RT Designer starts by compiling the algorithmic C code. A structure browser then highlights such features in the code as calls, loops and functions.

The software automatically maps the code to a minimal set of resources drawn from a hardware resource library that includes ALUs, adders, mu ltipliers, ROM, RAM and application-specific units that can be defined in terms of behavior. The library can be expanded with custom-written elements that may speed specific functions, such as specialized multipliers. "We license the library of everything you need to get started, in RTL VHDL and Verilog format. The tool creates the minimal data path and then analyzes the information," Beke said.

The reports and graphical tools in A/RT Designer tell the designer: the number of cycles required to execute each part of the code, resource and register allocation and utilization, variable lifetimes, register transfers and memory utilization.

Design options

This gives the designer a number of choices to improve the design depending on guiding priorities. "The designer can change the C code, change the architecture or change the resources," Beke said.

The scheduling of operations can be based on various strategies, such as ASAP (as soon as possible), ALAP (as late as possible) or "ALAP Gre edy."

ASAP tends to create faster operation but needs more storage and, thus, more die area and power consumption. ALAP, on the other hand, produces a slower schedule but uses fewer registers and is therefore smaller.

Among the enhancements in A/RT Designer is the addition of techniques like "loop folding"; "peephole optimization"; and "pipelining and speculation." The designer can use those techniques to reduce the number of clock cycles taken to achieve a necessary hard-real-time requirement or to minimize the resources required without breaching such a requirement.

Even for A/RT Designer, it is difficult, if not impossible, to provide absolute numbers for power consumption and die area, because the detailed structures have yet to be synthesized. But the tool does provide useful comparisons so that given the same logic synthesis flow, two architectures can be compared, according to Frontier.

A/RT Designer automatically generates both the C and HDL test benches, the company said.

A/RT De signer is available in two versions: A/RT Designer and A/RT Designer Pro. A/RT Designer Pro offers a wider variety of pragmas that provide a finer granularity in optimization. Both tools are available for HP-UX, Sun Solaris and Windows NT operating systems with licensing for A/RT Designer set at $65,000 per seat.