Altera targets DSP-based comms; ISS spins PCI core

Altera targets DSP-based comms; ISS spins PCI core
By Michael Santarini, EE Times
March 6, 2000 (10:25 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000306S0006

Altera Corp. (San Jose, Calif.) has stepped up efforts to increase its presence in the DSP-based communications market, releasing nine new error-correction cores for the communications systems market.

Altera said the new cores are built around the new Reed-Solomon Compiler, Viterbi Decoder and Turbo Encoder/Decoder solutions. The company said when implemented in an Altera programmable-logic device, the cores offer a low-cost performance solution for developing error-correction systems in current and emerging wireless applications such as digital video broadcast and various transmission technologies.

The company said the Turbo Encoder/Decoder solution is suited for error correction in next-generation wireless applications, such as the 3rd Generation Partnership Project (3GPP).

The core supports data rates in excess of 2 Mbits/second, appropriate for the high-speed data services required by emerging 3G systems. The Turbo Encoder/D ecoder has advanced technical features such as LogMAP algorithm for maximum error correction and includes a 3GPP-compliant interleaver.

Altera's Turbo Encoder/Decoder is targeted for use with the APEX 20K device family, fitting into an EP20K200E, priced at $43 in volume quantities.

The company's Reed-Solomon Compiler supports six different types of Reed-Solomon cores (including the standard encoder/decoder), an erasures add-on, continuous decoder and variable encoder/decoder.

The Reed-Solomon Compiler also supports the Consultative Committee for Space Data Systems standard, which is required for telemetry channel coding in wireless.

The compiler offers record encoding speeds of over 1 Gbit/s and decoding speeds of 800 Mbits/s.

Altera also offers a high-speed Viterbi Decoder core for applications requiring error correction. The core has a Viterbi Decoder rate of 100 Mbits/s. The Viterbi Decoder fits into an EPF10K30A, priced at $8.25 in volume.

According t o Altera, all the cores come with user guides. Customers can evaluate megafunctions for free prior to licensing via Altera's OpenCore feature, available at www.altera.com/Ipmegastore.

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Interconnect Systems Solution (ISS; Mission Viejo, Calif.) announced it has formatted its PCI core for the Reuse Automation system from Y Explorations (Lake Forest, Calif.).

The companies said the PCI-core-001 enables system-on-chip designers using the Reuse Automation tool to search for, select and integrate PCI functionality without extensive PCI bus-standards knowledge.

The YXI tools can generate and synthesize the interconnect (state machines, memory and glue logic) needed to integrate intellectual-property (IP) cores with any others in the YXI Reuse Automation-enabled database format.

Both companies intend to continue their collaboration to enable IP cores for Reuse Automation. Visit www.yxi.com or www.iss-us.com/.