IP conference will focus on systems within SoC

IP conference will focus on systems within SoC
By Michael Santarini, EE Times
February 22, 2000 (9:54 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000222S0009

IP2000 organizers have announced the final three-day program for the fourth annual Silicon Valley IP conference, which this year will focus on the systems within systems-on-chips. The show, jointly sponsored by sister publications Electronics Times and EE Times, will be held March 20-22 at the Santa Clara (Calif.) Convention Center.

The first day's program will be a business track organized by the publications. The second and third days will concentrate on technical issues with a program of keynote speakers, focused sessions, tutorials and panels.

IP2000's two-day exhibition will start on Tuesday, March 21. More than 60 companies are expected to participate.

Venture capitalist Rob Chaplinsky of Mohr Davidow will keynote the IP Business Forum on Monday. The business track, geared toward high-level executives and venture capitalists, will emphasize effective IP business models and infrastructure, according to the show organizers.< /P>

Five additional presentations Monday will be followed by a cocktail reception and dinner panel. The dinner panel will be on "The Changing Design Culture." Richard Goering, managing editor for EDA at EE Times, will moderate.

Also during dinner, Virage Logic will present the finalists of the second annual SoC Design Contest.

Tuesday's keynote speaker will be Theo Claasen, chief technology officer of Philips Semiconductor. Two technical session tracks will run concurrently. Track One will cover real-life case studies, the evaluation of IP quality and generators for IP. Track Two will focus on IP cores and integration.

The second day will also feature a luncheon panel on how to build a reuse culture within your company.

The show's last day will feature a keynote speech by ARM executive vice president Pete Magowan. Two morning tracks will look at C and high-level languages and methodology. The lunchtime panel will focus on breaking down barriers to IP reuse. The afternoo n will consist of three tutorial tracks.

In conjunction with IP2000, Virage Logic and Taiwan Semiconductor Manufacturing Co. are co-sponsoring the second annual SoC Design Contest, for systems that feature a creative use of embedded memory. The application categories are consumer, communications and computers, and the technology categories are nonvolatile memory, DRAM or other innovative memory structures.

There will be a $5,000 award for the winning entry, and TSMC will run a test chip of the winning design through the MPW process as part of the award package.

The finalists' designs will be on display at the Virage Logic booth. Conference attendees will be asked to select the winner in a ballot-style vote at the show. The results will be announced at the Virage booth on March 22, at 12:45 p.m.

The entry deadline for the Virage Logic SoC Design Contest is Tuesday, Feb. 29. For more information and an entry form, visit www.viragelogic.c om.

Attendees wishing to preregister for IP2000, or companies interested in exhibiting, can visit the IP2000 Web site at www.ip2000.com or they can e-mail Tony Hennie at thennie@unmf.com. Discounted attendance fees, in effect until March 5, are $395 for one day, $695 for two days and $795 for all three days. There is a $95 admission fee for the dinner panel discussion.