Panel probes SoC problems, solutions

Panel probes SoC problems, solutions
By Richard Goering, EE Times
February 2, 2000 (5:57 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000202S0044

SANTA CLARA, Calif. — Significant barriers to system-on-chip (SoC) integration persist in such areas as verification, on-chip buses, and mixed-signal design, according to participants in a panel discussion at this week's DesignCon 2000 show. But panelists also presented some in-house and commercial solutions to these problems.

Functional verification has become a "huge obstacle" for SoC design, said Martin Scott, ASIC business unit manager for Agilent Technologies. Even though intellectual property (IP) reuse has shortened design times, he said, verification has become a bigger percentage of the overall design cycle.

Scott said that challenges experienced by engineers at Agilent include verification of IP from extremely diverse sources; third-party models and test benches that don't work with system test benches; a lack of interoperability between verification environments; and a lack of standard methods for modeling, communication, synchronization, and error reporting.

Agilent has come up with a solution, however — a simulation environment that sits on top of Synopsys Inc.'s Vera verification product. Scott briefly described the benefits of this environment, which was discussed in more detail by three Agilent engineers in a paper given during DesignCon's technical sessions.

Scott said that Agilent's simulation environment allows for the rapid creation of test benches with reusable elements. It permits functional vector reuse at the block and system levels. It allows communication between a wide range of simulation models, and supports system-level analysis and hardware/software co-simulation.

Other internally-developed solutions to SoC problems were discussed by James Dickerson, director of SRAM and ASIC product development at IBM Microelectronics. He identified several key barriers: lack of standard interfaces, synthesis and timing closure, and verification.

Given the plethora of bus architectures, Dickerson argued that what's needed is common on-chip bus standards with compliance tests. The Virtual Socket Interface Alliance (VSIA) is working on a "bus wrapper" concept, but Dickerson said this will slow time-to-market and require a redesign of interfaces for cores built to comply with different standards.

IBM's solution is its CoreConnect bus architecture, an open standard that can be freely licensed. Dickerson noted that it actually supports two PowerPC-based buses — a high-performance, low latency bus for high data bandwidth, and a lower speed, low power on-chip peripheral bus.

In the verification area, Dickerson noted, IBM has developed a "test operating system" that schedules system-level tests and supports core-specific test applications. IBM has also developed its "Bondo" emulation chip, based on the PowerPC 405, to allow rapid prototyping of applications.

The rapid prototyping theme was picked up by Bob Payne, vice president for s ystem ASIC technology at Philips Semiconductors. The problem with SoC design, he said, is that there's no such thing as a perfect functional specification, thus forcing "rigid conformance to an ambiguous specification."

It therefore takes hours of real-time operation to know what an SoC can really do, Payne argued. But a Quickturn emulator will take 100 hours to replicate that one design, he said, while a cycle-based simulator will take 12 years and a time-based logic simulator will take a millennium.

Lopsided simulation

"No one would try to count a million dollars, but we task engineers with developing a million test vectors," Payne said. "Then we assume engineers know what they're doing." Those million test vectors, he said, might simulate 50 milliseconds of real-time operation.

The solution, Payne argued, lies with "deconfigurable and extendible platform architectures" that let users start with a reference design, and modify or swap out IP blocks as needed. Combining that approa ch with a silicon-based "benchtop" rapid prototyping environment such as Philips' Velocity system, Payne said, engineers can quickly verify SoCs and approach a 95 percent probability of first-time success.

The last frontier of true SoC design is the analog and mixed-signal world, according to Dennis Buss, vice president and director at Texas Instruments Inc. Today, he said, even people who talk about designing SoCs still typically place functions such as codecs, flash memory, and power management off-chip. Yet, Buss noted, we're entering an era where the communications and networking market is surpassing the PC sector, and bringing with it increased demands for DSP and analog circuitry.

"The challenge of analog integration is so high that a lot of people say you just can't do it," said Buss. "I say, just wait — this industry will." But some innovative new design techniques will be needed to make it all work, he said.

Want it, don't want it

In th e question-and-answer period of the panel discussion, Buss wasn't sanguine about the prospects of putting DRAM on-chip. "All of our customers want embedded DRAM, but none of them buy it," he said. Because customers don't want to pay ASIC prices for DRAM, and because of the increased process complexity, Buss said that off-chip DRAM will remain the solution in most cases.

Payne said that rapid prototyping can pre-prove mixed-signal interfaces in silicon. "SoCs should pull mixed-signal stuff onto the chip as well," he said. "Philips has a rich heritage in analog design, and we'll draw on that."

In response to another question about third-party IP, Payne noted that all of the major semiconductor vendors have found they need their own IP portfolios. "There really isn't a model of shopping the whole thing," he said. "It's more a case of augmenting your portfolio on a case-by-case basis."

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