Motorola releases reuse standards free via Web

Motorola releases reuse standards free via Web
By Michael Santarini, EE Times
January 3, 2000 (3:08 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000103S0041

Motorola's Semiconductor Products Sector (Austin, Texas) is offering free public access to three proprietary design reuse standards. The recently announced Semiconductor Reuse Standards (SRS; see Dec. 20, page 1), developed by Motorola's System-on-a-Chip Design Technology organization, comprise an intellectual property interface (IPI) standard, an IP and virtual component block deliverables guideline, and a Verilog HDL coding standard.

In releasing the standards on the Web, the company hopes the design community and independent vendors will develop soft cores that are fully reusable and compatible with Motorola's design methodology and architectures.

The IP interface standard covers the interblock communication needed in a system-on-chip design. According to the company, the standard provides interfaces for interprocessor, system and peripheral buses; global signals; test; and SoC I/O.

The approach calls for the use of "gaskets " to connect cores with those interfaces to Motorola's internal On Chip Buses. The interface for the peripheral bus gasket is very similar to the OCBs' peripheral virtual component (VC) interface, according to Motorola.

The company's IPI standard allows designers to connect modules to other compliant modules and to different CPU cores, accommodating bus widths from 8 to 64 bits.

The company said the IPI designates the set of required and optional signals, along with associated protocols, for such functions as interfaces to a peripheral bus or system test signals. The standard includes specifications and bus bridges as design aids, and bus functional models and bus monitors for verification.

The IPI standard defines a set of common architecture, micro-architecture and I/O signal standards for the design and verification of reusable system-on-a-chip modules. The first implementation of the standard targets only lower-performance, slave-only peripherals, which are normally connected to a peripheral bus. It includes the signals needed to provide basic slave cycles for communication with the rest of the system.

Future implementations are expected to include more ports for interrupts, global signals and DMA.

The Semiconductor Products Sector also released Verilog HDL coding and IP/VC block deliverables standards to let IP developers create Motorola-compliant soft IP that can interface to the company's core architectures.

According to Motorola, the Verilog HDL coding standard describes requirements such as coding styles, partitioning, naming conventions, allowed and disallowed constructs and testability aspects. The standard is based on the IEEE 1364.1 synthesizable Verilog subset, Motorola's direct design experience, and the Reuse Methodology Manual (RMM), developed by jointly Synopsys and Mentor Graphics.

The IP/VC block deliverables standard details the required IP deliverables for soft or hard IP and the respective data formats that need to be developed by t he IP creator and delivered to the IP integrator. The standard sets the expectations for the transfer of IP.

The SRS can be downloaded from www.motorola.com/semiconductors/srs.