Tera Systems' Tool Adopted by NEC Electronics for RTL Design Closure and Virtual Prototyping

Tera Systems' Tool Adopted by NEC Electronics for RTL Design Closure and Virtual Prototyping

Designers Given Early Warning of Design Bottlenecks, Performance Problems and Design Closure Issues at the RTL Level

CAMPBELL, Calif. - November 26, 2001 - Tera Systems today announced that NEC Electronics is using Tera Systems' TeraForm® RTL design planning product for design closure and virtual prototyping of customer designs. Tera Systems also announced that NEC Electronics will certify TeraForm and the necessary TeraGate[tm] libraries for customer use within NEC's supported design flows for ASICs and SoCs. TeraForm is used prior to synthesis to identify potential timing and area problems to aid in achieving RTL design closure. This results in smoother back-end design operation for NEC Electronics, and shorter time-to-market for NEC's customers.

 NEC Electronics and Tera Systems have worked together on library, tool and methodology refinements as part of a long-term goal of delivering early, rapid feedback on design quality to designers through creation of RTL-based virtual prototypes. NEC and Tera Systems engineers, through TeraForm, can assess complex design architecture issues and performance bottlenecks up to ten times faster than traditional "quick synthesis" techniques. This enables designers to understand the physical design implications of their design at a high level, where many design problems can be altogether avoided with relatively minor changes to the RTL. Since analysis with TeraForm takes place before gate-level synthesis, designers can expect to see equivalent or a higher level of quality and correlation with final silicon than with traditional design flows. TeraForm's interface to downstream synthesis and place-and-route tools, can substantially reduce runtimes by providing better starting points and eliminating wasted iterations.

 "NEC Electronics makes a practice of analyzing customer designs early in the design flow at the RTL to avoid downstream issues. This includes moving design hand-off to a higher level whenever possible, " said Kazu Yamada, general manager of NEC Electronics' Technology Foundation Group. "TeraForm's ability to help designers analyze their designs very early in the process makes adoption of this powerful tool crucial to modern SoC development. "

 As part of the certification of TeraForm, NEC Electronics and Tera Systems used the proposed IEEE standard Advanced Library Format (ALF) to build and characterize the TeraGate libraries used by TeraForm. ALF is an accurate and efficient representation of library elements that offers a unified format for timing, electrical and physical views. This vendor-neutral format is being used by leading-edge tool and methodology suppliers. It provides complete library characterizations that ensure correlation to silicon. Tera Systems will offer ALF interfaces on all future product releases.

" As one of the worldwide leaders in ASICs and SoCs, NEC is a very important customer and partner, " said Mark Miller, vice president of marketing and business development for Tera Systems. "Their experience and guidance has expedited the certification of our tools for use at NEC and greatly improved productivity for our mutual customers. "

 About Tera Systems
Tera Systems, Inc. is the leader in Hardware Description Language (HDL)-based design planning technology for use by designers of complex System-on-Chip (SoC) semiconductors. The company's products provide early visibility into design quality, performance, and manufacturability issues with the goal of preventing downstream problems with synthesis and physical design processes. Using Tera System's tools, SoC designers can ensure timing convergence and superior performance before reaching back-end layout or actual silicon where the costs of design errors or changes are extraordinarily high. Tera Systems partners with leading semiconductor vendors to develop highly predictable design methodologies and "golden" tool flows that dramatically accelerate the SoC design cycle. For more information, visit our web site at www.terasystems.com.