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New Xilinx Virtex-6 FPGA Family Designed to Satisfy Insatiable Demand for Higher Bandwidth and Lower Power SystemsVirtex-6 FPGA Family Built to Deliver More Computational Performance and Faster Networking at 50 percent Reduced Power and 20 percent Lower Costs "Competitive forces are driving infrastructure equipment manufacturers to focus on reducing system costs and operating expenses while next-generation applications across the spectrum of electronic equipment take up more bandwidth," said In related news, Built on a 40-nanometer (nm) process using third-generation Xilinx ASMBL(TM) architecture, the Virtex-6 FPGA family is supported by a new generation of development tools and a vast library of IP already available for the Virtex-5 FPGA family to ensure productive development and design migration. Providing 15 percent higher performance and 15 percent lower power consumption compared to competitive 40nm FPGA offerings, the new devices operate on a 1.0v core voltage with a 0.9v low-power option. These advances enable system architects to integrate Virtex-6 FPGAs into their designs to enable 'green' central offices and data centers, which is particularly relevant for the telecommunications industry as it implements the next wave of scaling to support demand for internet video and rich media content. Virtex-6 FPGA Domain Optimization The Virtex- 6 FPGA family comprises three domain-optimized FPGA platforms that deliver different feature mixes to best address a variety of customer applications:
A combination of advanced silicon technology, innovative circuit design techniques, and architectural enhancements enable Virtex-6 FPGAs to deliver significantly lower power consumption, higher performance, and lower cost than previous-generation Virtex devices and competing FPGA offerings. "With the Virtex-6 FPGA Family, Among the high-performance applications for which Virtex-6 devices are ideally suited are: Wireless Infrastructure - The higher densities and increased performance of Virtex-6 FPGAs, coupled with optimized IP developed by Wired Networking - Increased consumption of digital content is straining existing network bandwidth and accelerating development of next-generation applications, such as 40Gbps/100+Gbps line cards, routers, switches, and high-density data ports for data centers. The Virtex-6 FPGA family includes optimized logic ratios, increased performance for wider internal datapaths, and multi-rate transceivers to deliver higher overall throughput at lower latency. Using the Virtex-6 FPGA family customers can implement an OTU (optical transport unit)-4 framing and enhanced forward error correction (EFEC) solution used in core networks. Optimized logic and transceiver ratios enable developers to implement the 100-Gigabit Ethernet (GE) to OTU-4 framer and critical EFEC using Virtex-6 FPGAs. Developers can replace costly, high-risk Broadcast Equipment - Virtex-6 FPGAs provide a fully programmable, cost-effective solution for meeting current and future broadcast requirements, while enabling differentiation through video quality. High-speed serial transceivers support SD/HD/3G-SDI and embedded audio for all types of broadcast applications. Fully integrated support for 10Gbps Ethernet enables bridging between broadcast and telecomm networks allowing fast access and retrieval of stored video content. Increased memory and DSP ratios enable real-time, uncompressed video processing at HD, 2K, and 4K resolutions. Optimized logic ratios and power management enable advanced H.264 and JPEG2000 encoding, all while reducing power and thermal management requirements for any given performance target. Aerospace and Defense - Aerospace and defense designers are increasingly dependent upon FPGAs for high computational performance and reconfigurable computing in applications ranging from infrastructure communications to electronic warfare and image processing. Virtex-6 SXT FPGAs provide the industry's highest DSP bandwidth at over 1TMACS, by combining over 2000 advanced DSP slices with optimized ratios of logic, Block RAM, and distributed RAM. This computation bandwidth is augmented by over 450Gbps of serial bandwidth to move data on-chip and off-chip quickly and efficiently. All this computational capability is also fully scalable and optimized to reduce overall system power consumption by over 50 percent compared to previous generation technologies. Availability Device details and software support are available now through the Virtex-6 early access program. Initial Virtex-6 device samples will be available in the second quarter of 2009. To learn more or to get started on new Virtex-6 designs, system architects, system design managers and engineers can visit www.xilinx.com/6 or contact their About
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