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VIPswitch Selects Aldec's Verification Environment to Develop Industry's First Reprogrammable Terabit Router
VIPswitch Selects Aldec's Verification Environment to Develop Industry's First Reprogrammable Terabit Router
The continued commitment of both Aldec and Xilinx to deliver world-class EDA and silicon solutions allowed VIPswitch to produce the industry’s first switch/router with full reprogramming capabilities based on an FPGA device. Aldec's verification solution supports the complete range of Xilinx Virtex-II Platform FPGAs and provided a complete design entry and verification environment for VIPswitch’s Terabit switch/routers. The ability to modify the devices in order to accommodate the new demands of growing technology, as well as the added financial savings of using FPGA devices, prompted VIPswitch to use FPGAs in place of ASIC chips. After extensive evaluation and performance benchmarking, VIPswitch chose Active-HDL because of its integrated support of Virtex-II devices and clear path for supporting future generations of Xilinx FPGA devices. “We are pleased that VIPswitch chose Active-HDL in support of their next generation designs. VIPswitch is continually producing pioneering designs that incorporate the best tools in the EDA industry, and Active-HDL’s leading simulation performance helped contribute to their advancements in technology and their ability to bring the designs to market sooner,” stated Megan Moran, Product Marketing Manager for Active-HDL. "Xilinx and Aldec have a long-standing relationship that provides customers with the best solutions. Our companies work in concert to enable users to apply high performance verification techniques to their high-density designs, such as the one developed by VIPswitch. VIPswitch's manufacturing of the industry's first switch/router based on the Virtex-II Platform FPGA family illustrates how design engineers can use FPGAs as a cost-effective alternative to ASICs without compromising design quality, density, or performance," stated Rob Schreck, Senior Marketing Manager for Xilinx. “VIPswitch’s designs exceeded 20 million gates and were developed by a team of over 20 design engineers. The high performance and flexibility of Active-HDL provided us with a complete design environment for our complex project,” said Yvon Gaudreau, Senior Manager of Hardware Development at VIPswitch. “In addition to the decreased verification run times, Active-HDL allowed us to simulate VHDL and EDIF designs from a common kernel; the Source Revision Control and other advanced team-based features allowed multiple design iterations without jeopardizing the integrity of the design. The comprehensive verification solution provided VIPswitch designers with complete control of the entire process, and its integration with Xilinx products offered a single environment to design, verify, synthesize and implement our Xilinx FPGAs.” Availability About Aldec About VIPswitch Active-HDL is a trademark of Aldec, Inc. Virtex-II is a registered trademark of Xilinx. All other trademarks or registered trademarks are property of their respective owners ### Aldec Contact: Megan Moran VIPswitch Contact: Beverly Wilks |
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