Digital fingerprinting en route for IP cores

Digital fingerprinting en route for IP cores
By Michael Santarini, EE Times
May 10, 1999 (9:43 a.m. EST)
URL: http://www.eetimes.com/story/OEG19990510S0003

TAEUS (Take Apart Everything Under the Sun) Inc., a Colorado Springs, Colo.-based specialist in reverse-engineering and microcode-analysis projects, is launching a business creating digital fingerprints for intellectual-property cores, based on development work at the University of California, Los Angeles. Company president Art Nutter said that UCLA retains rights to the pending patents, but TAEUS will serve as a licenser and implementer of the fingerprint technology.

The second step in the plan to provide unique identifiers for cores is to create a software product that can read the fingerprints and identify when cores have been used in a system-on-a-chip design. A TAEUS team is developing a standalone fingerprint "reader" for NT or Unix environments, though the long-term goal is to make such a package an integrated part of a design environment from the likes of Cadence or Synopsys. Reading the behavioral design for fingerprints would take plac e after logic synthesis is completed.

TAEUS' involvement in what it calls its DFP program was almost accidental. The company regularly attends meetings of the Virtual Socket Interface Alliance (VSIA), because its reverse-engineering methodology is often used to track illegal use of third-party cores. An Actel Corp. representative told Nutter in early 1997 of a UCLA researcher, Miodrag Potkonjak, who had studied digital-fingerprint methods that did not require adding circuitry to a design. VSIA members seemed interested, Nutter said, but no one was willing to devote resources to the issue. TAEUS offered to take it on.

"The key is to define certain constraints in non-critical paths so that the creation of the ID does not add anything to the design in terms of latency," Nutter said. "It all is done at the level of writing code into a behavioral-level description of a design. In no way does this turn a soft macro into a hard one."

Nutter expects foundries, ASIC library houses and system m akers to be interested in fingerprinting their IP cores. The digital fingerprints will be readable in a soft configuration at logical level, and at a soft physical level using a GDS-II tape.

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ASIC library supplier Virtual Silicon Technology Inc. (Sunnyvale, Calif.) and Taiwan Semiconductor Manufacturing Co. have announced an 0.18-micron test chip that demonstrates the manufacturability of Virtual Silicon's TSMC-specific libraries using the 0.18-micron, six-level-metal process. The companies said the working silicon measurements show correct functionality and timing correlation with a difference of less than 5 percent between design-kit simulations and actual silicon performance. They added that I/O functionality and slew-rate control perform in line with simulation predictions. Also, reliability data exhibit more than 300-mA latch-up immunity at high temperature and over 4-kV electrostatic-discharge protection.

Evaluation kits for 0.18-micron libraries are available from Virtual Si licon immediately. Standard-cell and memory compilers will be ready in June. Test-chip reports are available to TSMC customers under non-disclosure with Virtual Silicon. Visit www.virtual-silicon.com.