Actel's Libero IDE v8.6 Continues to Lead the Way in Low Power Design and Analysis

New Version Also Features Design Debug

MOUNTAIN VIEW, Calif. -- August 03, 2009 -- Actel Corporation (NASDAQ: ACTL) continues to lead the way for low-power designs with the release of Libero® Integrated Design Environment (IDE) v8.6. The newest version of the Libero IDE offers designers several new features, including upgraded power analysis using the SmartPower tool and post-layout probe insertion for device debug. SmartPower v8.6 includes a new design analysis algorithm that provides a quick and accurate method for performing power analysis without having to utilize the traditional Value Change Dump (VCD) file. In addition, the new I/O Advisor identifies and suggests an I/O configuration that provides the least power consumption while meeting timing constraints. For more efficient design and debug, the new post-layout probe insertion feature allows designers to bring signals out to package pins for observation without needing to instrument within the design RTL and go through the synthesis flow.

"Power consumption is now the number one design consideration in many markets and applications, ahead of performance and cost", said Jim Davis, vice president of software and systems engineering. "With the enhanced features included in release 8.6, Actel strengthens its industry leading solutions for power optimization and analysis, and improves design cycle efficiency with easy to use probe insertion and signal observability".

A Closer Look at Libero 8.6 IDE

In SmartPower, the new vectorless power estimation provides power consumption results approaching the accuracy of a simulation derived VCD file in considerably less time. In the absence of simulation data, this feature provides better activity estimation than the traditional default toggle rate method.

Also within SmartPower, the I/O Advisor analyzes a design and suggests alternate output loads, drive strengths, and slew rates that, when selected, reduce I/O power consumption. The power consumption data is reported for both the current as well as the proposed options so the designer can easily ascertain the impact on power for the suggested alternatives. Designers can now test "what-if" scenarios to modify slew rates, drive strengths, and output loads in order to discern the optimal balance between power and timing.

For design debug, the probe point insertion feature enables designers to insert probes into the design after layout and bring signals out to package pins for analysis. Specific nets or clocks within the design can have probes added, edited and deleted. This real-time capability to view signals greatly enhances a designer's capability to pinpoint logic or timing problems. After the evaluation, the designer can easily revert back to the original saved design. Traditional debug methodologies require the designer to instantiate logic and probes within the design RTL and then run the design through synthesis and layout, which requires a substantial increase in debug time and system time to market.

Pricing and Availability

The Libero IDE can be downloaded and installed directly from Actel's website. The Actel Libero IDE Gold edition is available on Windows XP or Vista free of charge. The Actel Libero IDE 8.6 Platinum edition is available on Windows and Linux platforms for $2495. All editions are one-year renewable licenses.

For more information on Libero IDE: http://www.actel.com/products/software/libero/default.aspx

About Actel

Actel is the leader in low-power FPGAs and mixed-signal FPGAs, offering the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com.