Cypress plays PCI cores; NurLogic, IBM hook up

Cypress plays PCI cores; NurLogic, IBM hook up
By Michael Santarini, EE Times
February 1, 1999 (11:36 a.m. EST)
URL: http://www.eetimes.com/story/OEG19990201S0014

As FPGA vendors race to field 64-bit, 66-MHz PCI cores and the FPGAs to handle that level of performance, CPLD vendor Cypress Semiconductor Corp. has quietly slipped into the 32-bit, 33-MHz PCI market. The San Jose, Calif., company recently introduced what it calls "the first PCI 32-bit, 33-MHz cores designed specifically for CPLDs."

The cores in Cypress' new PCI library are zero-wait-state, VHDL-based PCI interfaces supporting 32-bit, 33-MHz PCI applications. The library includes three versions of the PCI Target design and two versions of the PCI Initiator design. Cypress said the smallest core uses 133 macrocells and will fit easily into a 192-macrocell device.

The cores run exclusively on Cypress' Ultra37000 family of complex PLDs. They are fully compliant with Rev. 2.1 of the PCI specification, according to the company.

The Ultra37000 family holds up to 512 macrocells, so users can select the core and device-density comb ination that offers the best combination of features and cost for their specific application.

Adding to the offering's flexibility, Cypress provides the cores to Ultra37000 customers in VHDL source code, which allows users-if they dare-to alter the cores.

Further, according to the company, users can integrate the cores into their designs with Cypress' Warp2 design software. Doing so offers the flexibility to place the core anywhere in the target device, Cypress said, as opposed to the fixed, device-specific modules offered by other vendors that require restricted placement within a device to meet performance objectives.

The company is providing the PCI cores as VHDL source code. Cores are licensed free exclusively for customers designing with Cypress' Ultra37000 CPLDs.

According to the company, its PCI Target cores are available now. The PCI Initiator cores will be available in the second quarter. Application notes and other information are posted at www.cypress.com/pld/cores/.

Privately held core and IC library vendor NurLogic Design Inc. (San Diego) has announced that IBM Corp. will offer NurLogic libraries and products to IBM semiconductor foundry customers without traditional non-recurring engineering (NRE) fees.

The companies said that under terms of the agreement, IBM customers will have access to NurLogic's full library of more than 1,000 elements of standard cells and I/Os, as well as its full spectrum of embedded memories, specialty I/Os and analog intellectual property.

NurLogic said it has electrically and physically optimized each component to IBM's 6SF 0.25-micron and 7SF 0.18-micron processes, and that it will provide direct distribution and technical support for the libraries.

Each component is accompanied by models and views for leading EDA design tools. In addition, NurLogic offers ASIC services to companies using its products.

Design kits for the IBM 0.25-micron process and preliminary kits for the 0.18-micron technology are available from NurLogic Design.