iWave announces the Host controller for SDXC card which is compatible with the SD Physical Layer specification V3.0

August 31, 2009 -- iWave announces the Host controller for SDXC which is compatible with the SD Physical Layer specification V3.0.The core developed, supports 32 bit AHB LITE Host interface working at SOC interface frequency and is compatible with the standard register set for the host controller as per SD host controller specification Version2.0. The core supports various modes of frequency of operation such as 200KHz, 25MHz, 50MHz and 100MHz making it suitable for wide range of applications for peripherals such as Bar code scanners GPS etc. for low speed application or multi media applications which need to operate at high frequencies. The core supports following UHS–I modes of operations.

• DS – Default speed mode upto 25MHz 3.3V signaling
• HS – High Speed mode upto 50MHz 3.3V signaling
• SDR12 – SDR upto 25MHz 1.8V signaling
• SDR25 – SDR upto 50MHz 1.8V signaling
• SDR50 – SDR upto 100MHz 1.8V signaling
• DDR50 – DDR upto 50MHz 1.8V signaling

The IP supports Data and response buffering. Data buffering is done by a 32bit FIFO with Dual-port RAM support. Response buffering is done through registers. Overall host Controller performance results in 100 MHz clock speed support in Actel (Fusion and PROASCI3) and Xilinx (Spartan3A) FPGAs.

The demo platform for the host controller is realized using Xilinx and Actel FPGA based platforms. The host interface in Actel is ARM based embedded CORTEX M soft core, in case of Xilinx it is microblaze based soft core.

Unlike the transition from SD to SDHC, which sometimes only required a firmware update, SDXC specification requires update in supporting peripheral system level set up also, e.g. for SDXC operation in SDR or DDR mode it is required that the SD signals from the Host controller change its operating voltage dynamically from 3.3V signaling to 1.8V. To achieve this in FPGA based platforms, extra I/Os and registers are included in the IP which will handle/control the external buffers that change the operating Voltage level as and when required.

The core developed supports following customizations

• FPGA: The design can be easily migrated to any specific FPGA technology as the modification/updation required is only in some FPGA specific macros like PLL/DCM and RAM instantiation
• Host interface: The standard core configuration has AHB LITE as the host interface. This can be easily migrated/changed according the required processor interface
• Applications: The end application of the SD Host controller may be vast. Hence the controller's features can be easily optimized to support the customers to fit in their specific design needs

About iWave Systems

iWave Systems Technologies is an embedded Hardware and Software Turnkey Design Services company, focused on providing integrated solutions for developing innovative products and systems in the areas of Communication, Consumer electronics and Multimedia.