Mentor Graphics Introduces SpeedGate Direct System Verification Environment for Rapid ASIC Prototyping

WILSONVILLE, Ore.--(BUSINESS WIRE)--Feb. 18, 2002--Mentor Graphics Corporation (Nasdaq:MENT - news) today introduced SpeedGate DSV(TM) (Direct System Verification)(TM), an advanced verification environment for creating application specific integrated circuits (ASIC) and System-on-Chip (SoC) prototypes using off-the-shelf field programmable gate arrays (FPGAs).

Silicon prototypes created by SpeedGate DSV can be tested at speeds comparable to a real-time operating environment, significantly reducing costly, time-consuming silicon respins. SpeedGate DSV adds a mid-priced ASIC verification technology to the industry's most complete verification flow that encompasses solutions from logic simulation to co-verification.

Today, ASIC verification consumes 30 to 70 percent of total ASIC design time. With costs for a 0.18-micron ASIC mask set exceeding $500,000, the financial impact of a silicon re-spin is substantial. Persistent budgetary and time-to-market pressures require a solution that reduces the verification cycle, while maintaining a high level of accuracy.

SpeedGate DSV addresses all hardware prototype creation and verification challenges, from partitioning, debug and interconnect to rapid board creation and analysis. By leveraging advances in commercially available FPGA technologies, SpeedGate DSV duplicates an ASIC design in an in-circuit environment. SpeedGate DSV provides in-circuit verification in a moderately priced solution, running three to four orders of magnitude faster than low-end tools.

"SpeedGate DSV provides one of the most sophisticated and robust environments for partitioning and debugging ASIC and SoC prototypes," Rich Sevcik, senior vice president and general manager, Xilinx, Inc. "Designers porting to our Virtex FPGAs using SpeedGate will find the most accurate representation of their designs in a cost-effective prototype."

"The versatility of SpeedGate DSV makes it a perfect complement to any existing verification flow," said Anne Sanquini, vice president and general manager of the HDL Design Division of Mentor Graphics. "For advanced flows making use of high-end emulation tools, SpeedGate DSV can be used to create low cost ASIC replicates that can be passed to software engineers for rapid system debug. For cost-constrained methodologies, SpeedGate DSV delivers close to at-speed system verification at orders of magnitude faster than low-end solutions."

About SpeedGate DSV

SpeedGate DSV is the most comprehensive and extensible solution for all aspects for the prototype design flow -- partitioning, debug and interconnect. It also links to board creation and analysis tools. An interactive design cockpit launches partitioning and synthesis tools, and the completely scriptable interface plugs into any ASIC design environment -- working hand-in-hand with emulation and gate-level simulation. SpeedGate DSV includes a patent-pending advanced partitioning technology that enables designers to minimize the number of FPGAs used to prototype a design. SpeedGate DSV fully supports the prototyping process with a team design environment, including sophisticated check-in/check-out features that track source code changes and manage version control. For more technical details, please see the enclosed technical overview.

Pricing and Availability

SpeedGate DSV is available now at a price of $98,500 for a floating license. SpeedGate DSV supports Sun Solaris 2.7 and 2.8 and supports ASIC partitioning on Xilinx Virtex FPGAs. More information can be found at www.mentor.com/speedgatedsv.

About Mentor Graphics Corporation

Mentor Graphics Corporation (Nasdaq: MENT - news) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $600 million and employs approximately 3,100 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.

SpeedGate DSV Technical Overview

Technology advances have made the prototyping of ASICs and SoCs with off-the-shelf FPGAs practical. But prototyping is a difficult process that involves many challenges. SpeedGate DSV is the only comprehensive and extensible solution for all aspects of the prototype design flow -- partitioning, debug and interconnect. It also links to board creation and analysis tools. An interactive design cockpit launches partitioning and synthesis tools and the scriptable interface plugs into any ASIC design environment, working hand-in-hand with emulation and gate-level simulation.

Superior Partitioning Capabilities

SpeedGate DSV employs a unique partitioning approach for logic and I/O among multiple FPGAs that addresses both I/O distribution and emulation prototype speed issues. Previous attempts to prototype at the module level proved too granular, making it difficult to provide balanced logic distribution. Other partitioning tools attempted to solve I/O distribution problems with a multiplexing scheme, which allows a single pin to handle multiple signals. This approach resulted in severe speed penalties, making true in-circuit prototyping impossible.

SpeedGate DSV solves the granularity problem by creating an intermediate level of granularity at the process level while maintaining the RTL database. The processes are "encapsulated" into individual entities that can move anywhere in the hierarchy. Moving encapsulated, highly connected processes can reduce the number of FPGAs required to prototype an ASIC design.

For some I/O intensive designs, the I/O count cannot be reduced beyond the pin count of the FPGA. The only way to continue the verification project is to get more utilization out of the pins available. One of the approaches to accomplish this is to add logic to the FPGA to make an I/O pin perform the function of multiple pins. SpeedGate DSV's I/O Management tool provides a wrapper feature that automatically creates logic to allow specific pins to handle multiple signals as defined by the user.

SpeedGate DSV includes a number of "helper tools" to speed up partitioning. For example, the Best Moves tool helps the designer reduce I/Os and LUTs in a design by displaying the best option.

Advanced Debug Capabilities

When a failure is detected with the ASIC prototype, verification engineers have to find out when, how and why it failed. This involves probing suspected RTL signals. But without a name preservation feature, the synthesis process changes the RTL signal names or optimizes the signals out. SpeedGate DSV includes a name preservation feature that assures all of the RTL signals for probing and observation are available.

Interconnect Compatibility Completes the Flow

Multiple boards are often required to prototype a complete ASIC design. The challenge to partitioning is to balance the logic between boards while limiting the interconnect between them. SpeedGate DSV supports all types of prototype boards: fixed-routed, reconfigurable, multiple and custom. Custom boards deliver the fastest prototyping boards but can be time-consuming to create. SpeedGate DSV does not require board description for a custom PCB layout, saving time in the prototyping process.

SpeedGate DSV has links to the Mentor Graphics board creation tools, which can be used to rapidly design a custom board. The company's integrated high-speed board analysis tools help designers perform critical path and other analysis.

Complete RTL Interactive Solution Simplifies Design Management

SpeedGate DSV provides a complete environment for unconstrained modification of the design at the RTL level. This environment features a single "cockpit" for source control, design management, design visualization, formal verification, synthesis, place and route and partitioning. Designers can import ASIC RTL into SpeedGate DSV and view files either as block diagrams or interconnect tables. From the same environment, design information can be exported for partitioning, formal verification and synthesis, simplifying overall design management. SpeedGate DSV also provides source control features, including check-in/checkout commands that help the design team manage multiple versions as well as track any changes to the source code.

Mentor Graphics is a registered trademark and SpeedGate DSV and Direct System Verification are trademarks of Mentor Graphics Corporation. All other company or product names are registered trademarks or trademarks of their respective owners.

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Contact:
     Mentor Graphics
     Athena Willems, 503/685-1400
     athena_willems@mentor.com
     or
     Benjamin Group
     Jason Khoury, 415/354-8391
     jason_khoury@benjamingroup.com